Blogs

Paolo Gargini—Intel Fellow, Technology and Manufacturing Group and Director of Technology Strategy for Intel—spoke on May 3 at the Semico Summit 2011.  He highlighted the time gap between when an idea is formed, to when the science, technology and engineering are able to make that idea a reality.  The incubation time for an idea to become real has shortened from several hundred years for satellites, to 12-15 years now for many ideas.

Dean Kamen, inventor and founder of DEKA and First, delivered the keynote address at the Semico Summit 2011.  He also received Semico’s Bellwether Award, granted annually to a visionary leader in the technology industry.  Dean has invented the insulin pump, a portable dialysis machine, the iBot mobility system, the Segway people mover, a prosthetic arm for DARPA, and a self-contained water cleaning and purification system, among other things.

The topic of Dean’s presentation was innovation, and how the United States is lagging behind in terms of educating and inspiring our youth to become innovators.  We take invention for granted because we have so much technology around us.  However, in developing countries, they are ready to take risks at much lower investment levels.

In the United States, we have the lowest percentage of kids going into science and technology in the world.  We also have the highest percentage of kids dropping out of high school in the world.  “Innovation should be thought of as a gift from one generation to the next,” Kamen said.

Dean believes we have a culture problem, where it is the tech industry, not lawyers and politicians, that needs to support a long-term serious commitment to science and technology.

In a May 2, 2011 presentation at the Semico Summit, Mr. Danny Biran, Senior VP of Marketing at Altera, discussed new opportunities as the boundaries between semiconductor logic device types become blurred. According to Mr. Biran, the boundary between FPGAs, ASICS, ASSPS and CPUs (MPUs, MCUs and DSPs has until recently been extremely well defined. 

FPGAs were customer programmable standard products.  Programming was developed for and owned by the customer.  ASICs used a standard cell design methodology.  The design was owned by the customer.  ASSPs were a standard high-volume product developed by the semiconductor vendor for sale to multiple customers.  MPUs, MCUs and DSPs were standard products, but the software needed to implement an application was developed by the customer.  Now, the boundaries between those categories are becoming blurred. Various semiconductor vendors are offering FPGAs with an on-board MPU, ASICs that include an FPGA block or ASSPs with multiple processing cores.  

The convergence of mobility, communication and computing has produced multifunctional end applications that are placing huge demands on semiconductor manufacturers.  These new devices require low power, high performance, and a lot  of advanced manufacturing capacity at a low cost.

At the 2011 Semico Summit, Gregg Bartlett, Senior Vice President of Technology and Research and Development, GLOBALFOUNDRIES talked about the economics of innovation, highlighting the daunting economic and technology challenges to bring products to market.  Just a few of the major costs include the following:

• $1-2 billion in leading edge process technology development,
• 3-4 years of development,
• $40-$50 million in chip design costs,
• $250 million for design enablement such as libraries and IP,
• $5-$7 billion for an advanced 300mm fab.

Today’s market is a high stakes game.  Its no wonder that the industry has embraced a collaborative environment at all levels.

At the just concluded Semico Summit 2011 conference, Sandeep Vij, President and CEO of MIPS Technologies made some very interesting observations regarding Consumer electronics applications and their use of memory resources. We all know that the feature sets and functionality of devices aimed at Consumer applications have been increasing over the last 3-4 years.

This is driven by the requirements of users of these devices for OEMs to deliver ever-increasing amounts of functionality like HD quality video, video downloads, touch screens, multiple HD cameras, personal video conferencing and multiple types of integrated sensors. Future requirements will include, but are not limited to, medical sensors, 100’s if not 1000’s of apps run in the devices, 3D-HD video, etc. These new levels of functionality must be fulfilled by placing higher levels of complexity into these silicon solutions to provide the right feature sets consumers desire.

All this takes an increasing amount of resources to deliver the right user experience. MIPS is the second largest CPU IP vendor next to ARM and is one of the first companies to see what these new levels of functionality demand in terms of the compute and system resources that must be placed into the system.

Semico Research Corp. was privileged to have the CEO of Xilinx Corporation, Moshe Gavrielov, deliver a presentation on developments in the Programmable Logic market at our just concluded Semico Summit 2011 conference. Moshe made some very interesting points that are not necessarily always connected to the programmable logic market:

In an a May 2, 2011 presentation at the Semico Summit, Mr. Len Perham CEO, MoSys, Inc. discussed looming problems in the processing of Internet traffic and offered a solution. According to Mr. Perham, Internet traffic will increase exponentially over the next three years, driven by applications such as video streaming, IPTV, P2P, cloud computing, social networking and VoIP + video.  Today’s traffic routing methods will not be able to keep up with that growth, and memory is the bottleneck. 

The problem is that today’s 40Gbps and 100Gbps packet processor line cards address memory on parallel connections, which will not be adequate at faster speeds beyond 100Gbps.  Routing data at those speeds will require a serial connection to the memory, not a parallel connection. MoSys has developed the GigaChip™ Interface, which is now an open standard supported by the GigaChip Alliance. 

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance.   It provides a fundamental performance breakthrough similar to the breakthrough achieved by DDR (Double Data Rate) DRAM.   The GigaChip Interface, using differential SerDes technology, is the next breakthrough in network processor to memory connections.  It allows a multiple-processor network processor to address multi-bank, multi-partitioned memory, so that each processor has access to memory without waiting.

Joe Sawicki, VP and GM of the Design-to-Silicon Division for Mentor Graphics, joined us at the Semico Summit on Tuesday to discuss scaling and the conversion to 3D.  He focused on a motto of “Willful Optimism” for the future.

Moore’s Law has been a cornerstone of our industry for 40 years, and a trend the speakers at the 2011 Summit were discussing was “More than Moore,” an idea that we are moving away from density to integration.  Joe Sawicki addressed this idea by discussing how scaling can only get us so far with advancing our speed and storage capabilities.  By 2026, he said, if we hold to Moore’s Law, we’ll be holding half a year’s movie collection on our phone.

In the future, Mentor Graphics believes we may be seeing the “e-Cube,” where we’ll have cubes of semiconductors instead of a die.

In discussing transitioning to 3D, there are cost and thermal issues, regardless of the advantages.  As a stepping stone, the industry can obtain many of the advantages of 3D by using 2.5D, a cost effective method to swing into the next generation.

The semiconductor industry grabs headlines as companies such as Intel announce the construction of multi-billion-dollar state-of-the-art research and manufacturing facilities. High performance servers, PCs and most of our electronic devices would not exist today if it weren’t for the continual advancements made in semiconductor manufacturing technology. While the most advanced chips supply the processing power and memory needed to provide the functionality and capabilities of our newest mobile devices and home electronics, they are surrounded and supported by dozens of other non-leading edge or mainstream semiconductor devices that play a crucial role in the electronics industry but don’t garner the same level of attention.

The vast majority of these mainstream semiconductors are actually manufactured on something less than leading edge technologies. Analog devices, sensors, microcontrollers, optoelectronics, discretes, MEMS and a number of other semiconductor products comprise the largest markets in terms of semiconductor units.

Can you hear me? I’m using a microphone on a 0.7mm2 MEMS die in a package measuring only 3.76mm x 4.72mm x 1.25mm. It’s the Akustica AKU230 digital, CMOS MEMS microphone, announced on March 30, 2010. For anyone who still doesn’t speak metric, the package size is less than 3/16” X 1/8” X 3/64.” For anyone still having trouble visualizing it, the package is smaller than a 14 point font capital “A” stamped out of a penny as a rectangle. In the simplest terms, really small. Of course, I’m not really using the Akustica AKU230, but I could be. It is used primarily in notebook computers, just like the one I’m typing on. The AKU230 is manufactured using conventional CMOS processes. The microphone membrane is a metal/dielectric layer, manufactured just like every other metal/dielectric layer in a CMOS process. The ADC circuitry is located around the membrane and is fabricated at the same time as the membrane during the same conventional CMOS processes. This approach offers savings in silicon area compared to a MEMS microphone fabricated using more traditional MEMS processes. Some MEMS microphones have an analog audio output. Some have an analog audio output but can provide a digital output using a second semiconductor, essentially an ADC. Akustica MEMS microphones, including the AKU230, are the only MEMS microphones that combine the microphone and the ADC circuitry on one chip, offering a simpler, less expensive solution and one insertion cost rather than two.