Semico is a semiconductor marketing & consulting research company located in Phoenix, Arizona. We offer custom consulting, portfolio packages, individual market research studies and premier industry conferences.
Major semiconductor foundries have revealed their advanced technology roadmaps for the next few years. They’re all investing billions of dollars into the development of process technologies and packaging options. The number of alternatives has been described as ‘dizzying’. How can all the foundries remain profitable? How does the customer decide which ‘route’ to take?
For the twenty-year period from the mid-1980s through the mid-2000s, process technology nodes were relatively easy to segment. Semico forecasted wafer demand into very clear process technology categories. Starting with the 45/40nm node in 2007, the two major logic manufacturers (Intel and TSMC) along with competing foundries began taking different paths. But the paths were still relatively clear. Intel rolled out their 45nm technology, and then TSMC rolled out their 40nm process. The foundries began to focus on low-power processes first. Then they followed up with their high-performance process several months to a quarter later.
Today, in addition to the number of different nodes, the challenge includes Intel’s claim that their 10nm process is comparable to the 7nm offered by other foundries. Semico believes the matching of product needs with process performance and cost will dictate market acceptance, not the marketing claims of technology-naming convention.
Semico Research would like to announce that Rich Wawrzyniak, Senior Analyst, will be speaking at DAC 2017 in Austin, Texas. The Design Automation Conference will be held June 18-22, and Rich will be speaking on Wednesday, June 21. He will participate in the panel "Have Third Party IPs Killed Internal IP Development?", led by Ann Steffora Mutschler from Semiconductor Engineering.
Semico Research is pleased to announce Jim Feldhan, President of Semico Research, will speak at the Center for Economic Growth's premier 87/90 Semiconductor Summit in New York on June 8. Mr. Feldhan will present a keynote talk about economics and forecasts for end markets.
published by Rich Wawrzyniak on Thu, 2017-05-25 21:01
Interview with a Power Management Architect
by Richard Wawrzyniak: Principal Analyst; ASIC and SoC Semico Research Corp.
Dynamic Power Management has become a 'must-have' in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.
Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel.
The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today.
Market Requirements Drive Power and Energy Targets
Today, there is a constant evolution in market requirements for silicon solutions targeted at mobile applications. This is primarily driven by user demands for more functionality while delivering greater ease-of-use to the end user. All these advanced features and increased functionality come at a price; greater power consumption and rising device complexity.
If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design costs), the overall impact can be similar. In this case, the number of design starts is impacted by the climate of rising design costs.
The SoC market has become the largest segment of the worldwide semiconductor market and is expected to reach $169.8B by 2021, a 7.7% CAGR. The adoption of the SoC design methodology has allowed the creation of very complex silicon solutions with rich feature sets and functionality. However, the predicted end of 'Moore's Law' is looming over the industry as improvements, once taken for granted through process geometry gains, start to become much harder to achieve at each new process node.
No question, 2017 is expected to be a good year for the semiconductor industry. Semiconductor revenues for 2017 are expected to increase over 9% this year. A 6% increase in unit sales, as well as higher average selling prices for memory products, will help drive the revenue growth rate to its highest level since 2010. Wafer demand is forecast to grow by almost 8%. The higher revenue growth compared to units and wafer demand is a welcome change compared to the last two years. But there are a couple clouds on the horizon.
The strong unit growth over the past several years has been at the expense of falling average selling prices. New MEMS and sensor products, the driving forces behind IoT, have experienced steep declines in ASPs. The industry is very familiar with the declines in DRAM cost per bit and how that drives increased applications and demand for memory. Comparing MEMS and sensor ASP declines to that of DRAM, there is a close correlation between the two. In fact, between 2010 and 2016 sensor ASPs fell faster than DRAM cost per bit over the same timeframe.
The Wafer Demand Summary and Assumptions is a quarterly publication. It includes an excel spreadsheet with annual wafer demand by product by technology from 2010-2021. Product categories include DRAM, SRAM, NAND, NOR, Other Non-volatile, MPU, MCU, DSP, Computing Micro Logic, Communications, Other Micro Logic, Programmable Logic, Standard Cell, Gate Array, Analog, Discrete, Optoelectronics, Sensors and Digital Bipolar. In addition, there is a summary write-up providing the major assumptions behind the forecast and changes from the previous quarter.
Where is the semiconductor manufacturing sweet spot? Two recent Semico Research Corp. studies provide the information to not only determine the overall sweet spot but to dig even further to find which products and technologies are the driving forces behind the growth or decline.
Chart 1, below, was developed from data in the fab database study. It shows the number of fabs operating and planned by wafer size.
published by Morry Marshall on Sat, 2017-04-15 00:13
Semico Research has just released a mature technology market research study. Wait! Mature technologies? Aren’t those fabs trailing-edge technology, old hat, passé? They may use older technology, but there’s a lot of action there now.
For many years, semiconductor manufacturing has tended to migrate from older fabs to newer fabs in a predictable manner. Leading-edge semiconductors such as processors and memory migrated to leading-edge fabs. ASICs and other integrated circuits migrated to the second-generation fabs just vacated by the leading-edge parts. Discretes and other trailing-edge devices migrated to the third-generation fabs. Older fabs were decommissioned. That pattern ended several generations ago. The reasons are complex. It involves economics, diverging memory and logic technologies, new applications which require low power, and market dynamics which include company consolidation.
