Today, chip designers craft their semiconductor products to meet ever-increasing market demands for lower power, higher performance and lower costs. While chips may meet system specifications, these complex designs require even more attention at the packaging and board level to obtain the full benefit of the chip design. Performance, power dissipation and formfactor challenges require a rechanneling of system design effort away from merely implementing ever more-complex silicon solutions towards dealing with complex applications from a system integration point of view. The rollout of 3D, 2.5D and silicon interposers adds yet another dimension. The new model must incorporate tasks that had previously been accomplished in silos and once held as separate functions. The creation of the system solution now requires planning chip design with packaging and PCB layout to create the optimal end application.
On October 13th, 2015, industry experts met at the Semico Impact conference for discussion, insight, and collaboration to enhance system-level design, performance and cost savings with first time right solutions. Boards, Chips and Packaging: Designing to Maximize Results was well-attended by board designers, system architects, chip designers, package designers, program managers, and marketing executives involved in the system-level ecosystem decisions. A highlight of the day was a keynote by Captain Chesley B. "Sully" Sullenberger, best known for serving as Captain during what has been called the "Miracle on the Hudson". He is known for his expertise in safety and knowledge of improvements of high-performance systems to save lives, save money and bring value to communities.
Venue: Biltmore Hotel & Suites, Santa Clara, CA
Date: Wednesday, April 23rd, 2014
Register: $75 at the door. Online registration has closed.
The Smart Lighting Series will focus on the revolution of the Solid State Lighting (SSL) industry and how it relates to building automation and the Internet of Things (IoT).
Identify key trends in building automation and how smart lighting will drive commercial and retail adoption. Address key questions:
As the development of solid state lighting (SSL) continues to advance, it opens the possibilities of integrating sensors, controls, connectivity and communications into luminaires. As individual luminaires become smarter, the opportunity to integrate them into cost-effective smart buildings, automobiles and other applications emerges as a profitable business opportunity. Commercial real estate offers one of the largest market opportunities for smart lighting, though ironically, SSL has made the least penetration into the commercial office lighting space.
And you won’t want to miss Light Think Studios, DainTree, Intematix, and Luminus Devices as they open a discussion on the panel entitled Smart Lighting: The Gateway to IoT? The panel will be moderated by Konstantinos Papamichael, Co-Director of the California Lighting Technology Center at UC-Davis.
The Semico Summit is an annual executive conference focused on strategic issues of major concern within our industry. Widely revered as the semiconductor event of the year, the Summit has been in existence since 1997. There are ample opportunities for interaction with top-level leaders in a casual setting. Traditionally, the event kicks off Sunday with a golf tournament & welcome reception. A well-attended president’s dinner follows Monday's sessions where the industry's best and brightest gather through Tuesday afternoon. Hot button issues are pressed with featured presentations delivered by internationally recognized leaders and followed by lively Q&A sessions.
Doubletree Hotel, San Jose, CA November 6, 2013
To see videos of the speakers, click here.
Semiconductor IP continues to be a crucial component in the design and development of complex integrated circuits, especially SoCs. This Semico IMPACT Conference will focus on the IP ecosystem and issues that are affecting the growth of the semiconductor industry.
From Basic SoCs to Advanced Performance Multicore SoCs, designs are evolving into new forms, enabling a variety of enhancements to existing end applications.
IP subsystems, the holy grail or marketing hype?
Changes in the IP market are prompting enhanced and more comprehensive tool sets from the EDA vendors. What can we expect in the future regarding more highly integrated and intelligent EDA tools to aid in infusing more complex IP blocks into SoC designs?
As designs become more complex, so too has the size of the verification effort. What is the current understanding of EDA vendors of this issue and what can be done about it? Where will it be in the near future? What do EDA and IP vendors see as the future of verification IP in relation to the total design effort? Will verification IP ever be used in the design of the SoC silicon itself?
The Semico IMPACT Conference “Focus on the IP Ecosystem” will provide a lineup of thought-provoking keynotes and enlightening panels. If you are a silicon architect, an SoC designer or an ASIC design manager, plan to attend this event on Wednesday, November 6, 2013 at the Doubletree Hotel in San Jose, California.