Rich Wawrzyniak is Semico's Senior ASIC and SoC Analyst.  See his bio here.

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Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect
 
by Richard Wawrzyniak: Principal Analyst; ASIC and SoC
Semico Research Corp.
 
Dynamic Power Management has become a 'must-have' in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.
 
Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel.
 
The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today.
 
Market Requirements Drive Power and Energy Targets
 
Today, there is a constant evolution in market requirements for silicon solutions targeted at mobile applications. This is primarily driven by user demands for more functionality while delivering greater ease-of-use to the end user. All these advanced features and increased functionality come at a price; greater power consumption and rising device complexity.
 

Impact Of Rising SoC Design Costs On Innovation

(Originally published at semiengineering.com)

If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design costs), the overall impact can be similar. In this case, the number of design starts is impacted by the climate of rising design costs.

Following are a few of Semico’s findings.

Cadence CDNLive Keynote Address: Thoughts and Implications

I attended the Cadence CDNLive conference at the Santa Clara Convention Center on April 5 and 6, 2016 and had a chance to listen to four very thought provoking presentations given by the speakers. These presentations were combined to follow the keynote address given by Cadence CEO, Lip-Bu Tan and addressed several different aspects of the current semiconductor industry landscape.

Speakers
• Lip-Bu Tan, CEO, Cadence Design Systems
• Steve Mollenkoph, CEO, Qualcomm
• Sanjay Jha, CEO, GLOBALFOUNDRIES
• Tom Beckley, Sr. Vice President and General Manager, Custom IC & PCB Group

The Increasing Demand for High Speed Communications Channels

If there is one constant in our mobile, connected society today, it is the continual demand for moving more data, more efficiently and at less cost.  This dynamic underscores virtually every technology and end market. It is a trend that is proving to be critical to the semiconductor industry as well as companies like Facebook and Google that participate in the efforts to create the standards necessary to deploy 400G data channels for data centers.
 
The high speed channel initiative is aimed at the data center. It is a certainty the high targeted speeds will allow more data to be moved more quickly into edge devices and eventually smart phones, tablets and other mobile devices. While the transition to these speeds by devices is still in the future, there is market pressure to increase the data communication capabilities of the SoCs in mobile systems.
 

What I Learned on the Way to the Semico Impact Conference: Focus on the IP Ecosystem

I had a very interesting discussion with Sundar Iyer, CEO of Memoir Systems, during a briefing they gave Semico on their just-released Pattern Aware Memory IP technology.

To briefly restate their announcement: Memoir has researched the different interactions between processors and memory in high-performance datacom systems and found that certain operations recur fairly often.  These operations roughly fall into four groupings: Counter Memory, Sequential Memory, Allocation Memory and Update Memory.  There are probably many more than these types, but Memoir is starting with these operations to begin with.

Memoir Systems is a 3rd party memory IP company and, as such, devotes its time to developing and introducing embedded memory IP to the market. In the case of this new product announcement, the memory IP they are introducing is tailored around the four functions mentioned above. In other words, their memory IP is now configured to better support these specific operations at the memory level and not through software at the processor level in the system. This has large implications for system performance and throughput.

New World Applications and the Role of IP

Electronic devices have evolved from cyclical killer applications to everyday ‘must-have’ tools.  Smartphones and tablets are a couple of these ‘must-have’ devices and are already making possible new world applications.  Many of these new world applications, including the Internet of Things and mobile health, will be pervasive and promise high semiconductor unit volumes.  Semico has identified 70 appliances in the average home that can become part of the Internet of Things.  Before we experience the hockey-stick growth in these markets there are a few hurdles to overcome: 

Where Have All the IP Vendors Gone? Part 3: Market Consolidation

We have answered the first two questions on Market Growth and Market Maturation. The third question relates to Market Consolidation and its impact on the long term health of the 3rd Party IP market.

Does the fact that we have recently seen several ‘large’ IP companies acquired by other ‘larger’ IP companies mean the long anticipated consolidation in the industry has gotten underway.

In order to answer this question it might be a good idea to consider what conditions contribute to, or force, a market consolidation in the first place:

Where Have All the IP Vendors Gone? Part 2: Market Maturation

Well, we have answered the first question about market growth, now how about market maturation?

Market maturation can be viewed in two ways:

Where Have All the IP Vendors Gone? Part 1

Well, the title is a little facetious, but given all the recent acquisitions in the 3rd Party IP market, it may certainly feel like that to some people. You can relax, there are still plenty of IP vendors left in the market and that won’t change anytime soon.

So what is going on?

  • Does this foretell a slowing in the market growth so the smart people are getting out now?
  • Is this the start of the long prophesied market maturation?
  • Are we finally seeing the so-called market consolidation down to 4 IP vendors?

I can’t tell you how many times I have heard these questions over the last 10 years. It seems like anyone with an opinion on these issues usually speaks up when certain activities occur – like one IP vendor being acquired by another IP vendor. Or people see the acquisitions as a sign that the IP market can’t keep growing at the same rate as the last 3-4 years, which by the way was really quite good. In fact much better than the overall semiconductor market.

Let’s start by looking at the 3rd Party IP market growth over the last several years.

3rd Party IP Market Growth Rates: 

Is Nanotechnology a Wellspring of Innovation or a Blind Alley?

It’s that time of the year when everyone recaps what occurred during the current year and looks forward to possible developments and trends for the coming year. Dr. Wally Rhines, CEO of Mentor Graphics and industry luminary,  posted an article in EETimes on 11/28/12 looking at previous advances in the semiconductor industry and how, if these trends continue, they might impact our industry looking 40 years out in time. Dr. Rhines brought some amazing metrics to light:

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