Rich Wawrzyniak is Semico's Senior ASIC and SoC Analyst.  See his bio here.

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Rich Wawrzyniak's blog

Is Nanotechnology a Wellspring of Innovation or a Blind Alley?

It’s that time of the year when everyone recaps what occurred during the current year and looks forward to possible developments and trends for the coming year. Dr. Wally Rhines, CEO of Mentor Graphics and industry luminary,  posted an article in EETimes on 11/28/12 looking at previous advances in the semiconductor industry and how, if these trends continue, they might impact our industry looking 40 years out in time. Dr. Rhines brought some amazing metrics to light:

Sonics and the Semico IP Ecosystem Conference

Grant Pierce, Chief Executive Officer, Sonics, Inc., gave a keynote presentation at the Semico Impact Conference: Focus on the IP Ecosystem on May 16, 2012.  His presentation that looked at the rise of cloud computing and its impact on the SoC market. Today, consumers expect connectivity ‘Anytime, Anywhere’ and can mostly get what they want over the various networks in the market today. However, as more of that connectivity functionality that resides in the ‘cloud’, increases in device performance are necessary to keep pace with the rich features that reside in the cloud. This puts pressure on SoC design and SoC architectures. Cloud-scale devices are driving SoC complexity due to the following market demands.

Synopsys and the Semico IP Ecosystem Conference

John Koeter, the Vice President of Marketing, for the Solutions Group at Synopsys, Inc., gave a presentation at the Semico Impact Conference:  Focus on the IP Ecosystem on May 16, 2012 that looked at the changes occurring in the market today caused by the rise in mobile devices. First, he started of by giving some metrics on the mobile market captured by Cisco.

Cadence Design Systems and the Semico IP Ecosystem Conference

Semico held its Impact conference: Focus on the IP Ecosystem at the DoubleTree Hotel in San Jose, CA on May 16th,2012.  The day before, on May 15th, Cadence Design Systems announced its first IP Subsystem product, a Storage IP Subsystem based around the new NVMe (Non Volatile Memory express) interface standard for flash-based storage applications completed in March, 2011.  This IP Subsystem provides a complete HW / SW verified solution and maximizes the command throughput for interaction between system software and the storage system.

It is intended for those applications that want to replace rotating media in a system with flash-based Solid State Drives (SSD). Vishal Kapoor, Vice President, Marketing Design IP and Services at Cadence gave a presentation at the Semico conference the very next day. He provided some fascinating insights into the forces at work behind the creation of their Storage IP Subsystem.

The IP Subsystem Race is On

Designers at large IDMs first created their own IP Subsystems out of the discrete IP blocks they were already licensing or had developed internally.  This was done to both reduce the level of effort they were expending to create a certain level of functionality and to increase the performance of these discrete blocks in the design. This process has been occurring for the last 4 – 5 years as a captive activity at several of the larger IDMs around the world.

Now, for the first time, major IP Vendors are starting to offer their own IP Subsystems as products available from the 3rd Party market to designers at companies of all sizes. The IP Subsystem as a product is the embodiment of the desire by silicon designers to move up a layer of abstraction and to design with system-level functions instead of licensing many discrete IP blocks and aggregating them into the system-level functionality they need for their silicon solutions. By approaching the design flow in this manner, a great deal of time and cost can be removed from the design effort. There are several potential benefits to designers in adopting this approach:

Sandeep Vij, President and CEO of MIPS Technologies

At the just concluded Semico Summit 2011 conference, Sandeep Vij, President and CEO of MIPS Technologies made some very interesting observations regarding Consumer electronics applications and their use of memory resources. We all know that the feature sets and functionality of devices aimed at Consumer applications have been increasing over the last 3-4 years.

This is driven by the requirements of users of these devices for OEMs to deliver ever-increasing amounts of functionality like HD quality video, video downloads, touch screens, multiple HD cameras, personal video conferencing and multiple types of integrated sensors. Future requirements will include, but are not limited to, medical sensors, 100’s if not 1000’s of apps run in the devices, 3D-HD video, etc. These new levels of functionality must be fulfilled by placing higher levels of complexity into these silicon solutions to provide the right feature sets consumers desire.

All this takes an increasing amount of resources to deliver the right user experience. MIPS is the second largest CPU IP vendor next to ARM and is one of the first companies to see what these new levels of functionality demand in terms of the compute and system resources that must be placed into the system.

CEO of Xilinx Corporation, Moshe Gavrielov

Semico Research Corp. was privileged to have the CEO of Xilinx Corporation, Moshe Gavrielov, deliver a presentation on developments in the Programmable Logic market at our just concluded Semico Summit 2011 conference. Moshe made some very interesting points that are not necessarily always connected to the programmable logic market:

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