Potential Design Cost Savings from using AI Tools for SoC Designs Ranges from 20% to 30%, says Semico Research

The semiconductor industry today is faced with several substantial issues—the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of complicated software applications intended to run on the SoC silicon. As happens often in our industry, the right solution surfaces at the right time. That solution is the incorporation of AI functionality into existing EDA tools as an aid to silicon and software designers and to make these designers more efficient and productive. A new report from Semico Research, New Directions in the EDA Market: Designing with AI Tools (SC109-20) projects that initial potential cost savings from using such tools for SoC designs ranges from 20% to 30%.
 
"Currently AI functionality is being added to EDA tools in the form of add-on modules. This is both the fastest and most cost-effective method of deploying these capabilities in the short term," says Rich Wawrzyniak, Principal Market Analyst for ASIC & SoC at Semico.  "The idea is to make the existing tools better with the least amount of disruption. We believe that most companies will eventually re-architect their tools to incorporate the AI functionality as a standard feature. In a uniquely ‘semiconductor industry inspired solution’, we are using technology – AI - to solve a problem caused by technology – rising design costs"
 
Key findings of the report include:

• Semico forecasts the penetration rate of tools with AI functionality into the EDA market will reach 47.8% by 2025, a CAGR of 33.8%
• Currently, the penetration rate is 6.2%, but will grow quickly as the industry transitions from add-on AI modules to fully featured AI EDA tools
• Use of AI-enabled tools allowed a reduction of 21.3% on a representative SoC design at 14nm
• AI-enabled EDA tools can be used on older geometries, but savings may be less due to lower overall levels of design effort needed to accomplish the design

In a unique, insightful look at this constantly evolving market, Semico Research's new report, New Directions in the EDA Market: Designing with AI Tools (SC109-20), examines the impact of AI on chip design and is segmented into three parts:

• Part One: Briefly details the rise in device complexity for SoC designs of all types and gives relevant industry metrics to gauge issues and progress.
• Part Two: Details the current state-of-the-art features in EDA tools and focuses on tools with some level of AI functionality.
• Part Three: Takes primary and secondary research that Semico has developed over the years and walks through a representative SoC design from the standpoint of design costs, market size, return on design investment, unit volumes, revenues and profitability.

For more information, contact:
Rick Vogelei
Phone: (480) 435 - 8564
Email: rickv@semico.com