Michell Prunty's blog

In recent weeks Akustica has made two major announcements. One is a high definition microphone and the other the world’s smallest microphone.

The high definition voice product is aimed at the emerging demand for higher bandwidth for VoIP. Akustica is in discussions with Skype and Google Talk.

The smallest microphone is the result of a die shrink that resulted in a 70% smaller die. Akustica claims that it can reduce the price to meet the cost requirements of the cell phone market and even exceed expectations. The package measures 1mm x 1mm.

Semico Spin

Akustica first emerged a little over a year ago. What has always been notable about the company is that all of its products use standard bulk CMOS. This is impressive in the MEMS market where well established companies have there own special processes. The microphones have CMOS logic integrated onto the MEMS.

Akustica’s early design wins have been in the notebook PC market, with systems available in 2007. Growth is being driven by such applications as VoIP, web cams, and Youtube. With the latest product announcements it is apparent that Akustica will broaden its target markets to include cell phones.

It appears to Semico that Akustica is offering a compelling solution that can reduce not only cost, but also size constraints as well as offer improved performance.

Last week Microchip Technology announced further expansion of its burgeoning 16-bit product line. Microchip has become the leading vendor of 8-bit MCUs. However, it is also growing in the 16-bit MCU space with both standard MCU and Digital Signal Controllers (DSC) which are MCUs with DSP functionality. The new products are PIC24 and dsPIC33.

Microchip is targeting the smart sensor and motor control markets with these devices. The company offers a seamless path among its PIC24 and dsPIC product lines enabling customers to trade off price, performance, and features. The dsPIC33 offers self-calibration for the sensor market. There are motor control versions which integrate several power functions such as PFC and load control. The general purpose versions offer CAN.

One key element in the recent announcement is Field Oriented Motor Control. This is an algorithm Microchip provides for free. It runs on the dsPIC12MC202. This algorithm provides complex control of such motor control features as torque control, noise reduction and power efficiency.

Semico Spin

Last week Semico had the opportunity to visit Interop at Mandalay Bay. With over 400 exhibitions, it was hard to pick a favorite, so here are some of the products that caught our attention.

For enterprise solutions the AdderLink ipeps (IP-engine-per-server) stood out among the KVM switches. A KVM-via-IP product, the palm-sized AdderLink ipeps enables computer access from any location via the internet or a corporate network.

Phihong USA demonstrated their PoE workstation using their POE60U-560G and POE45D-120 products. PoE workstations are targeted to schools, call centers, brokerage houses, and emergency services for its cost savings and single point of backup in case of a power outage. Using the IEEE 802.3at standard, their products deliver 60watts over a PoE cable, enough power to run the workstation and monitor.

Fujitsu announced their next mobile WiMax SoC, touting substantial speed and performance improvements. Additionally, Makoto Awaga said, “we are confident we will be able to achieve the lowest power consumption for this class of device.” Any product update that can provide increased performance with low power is a good thing, but in the mobile WiMax market, media rich applications are desperate for increased performance to help this emerging market take off.

On May 22, 2007, STMicroelectronics, Intel, and Francisco Partners announced an agreement to create a new memory company. This company will combine Intel’s NOR assets with ST’s NOR and NAND business with the financial acumen of Francisco Partners.

Rumored to be in the works for months, the new company combines the NOR revenues of the number two and three players in the market to take the top position away from Spansion. However, Spansion hopes to benefit from the new competition. Intel and ST’s NOR businesses, like others in the market, have not been profitable for some time.

Without the deep pockets of the larger companies, the new company won’t be able to compete with the heavily discounted prices seen recently in the NOR market. It’s possible that the consolidation will help Spansion turn a profit, once prices rise back to normal levels. They are very well positioned for profitability with the 300mm SP1 facility in Japan coming online and a host of cost-cutting initiatives already in motion.

There has been a need for consolidation in this industry for some time. Semico believes that between the Intel/ST venture and Samsung gunning for domination, there will be some smaller manufacturers who will either drop out of the market altogether or will sell off their NOR businesses to one of the larger companies.

This week Renesas presented the technology roadmap for a new MCU architecture. At this time this is more of a pre-announcement. The company expects the specification to be complete by 2Q 2008 and first samples will be available by 2Q 2009.

When Hitachi and Mitsubishi merged their semiconductor operations to form Renesas a few years ago it became the number one MCU vendor for 16-bit and 32-bit MCUs. This was the result of combining the H8S/SX and the M16C/32C families. Renesas management promised to support both product lines equally. In the ensuing years this promise appears to have been kept.

Renesas is now looking to further solidify its position in high end MCUs. The new MCU architecture will in fact be a merger of the H8S/SX and the M16C/32C families. The goal will be to make this new 16-bit and 32-bit MCU architecture be compatible with the company’s existing MCU families. Renesas will offer a unified peripheral set. Both application specific and general purpose versions will be offered. There is no brand name for this new MCU at this time.

This week MIPS announced the MIPS32 74K core, a next-generation processor core family offering an innovative embedded microarchitecture. It is the industry’s first fully synthesizable 32-bit processors to achieve operating frequencies greater than 1 GHz in TSMC 65nm process technology.

The MIPS architecture has a dominant position in high end consumer electronics, in particular DTV, Set top box, IPTV, DVD players/recorders (including Blu-Ray and HD DVD), residential gateways and VoIP. These applications are also part of the convergence trend of communications and CE. These and other emerging applications are driving the demand for increasing performance, as well as lower system costs and low power consumption. The 1 GHz performance cited by MIPS is critical.

Also important for SoC designers is that the 74Kcore family is designed to work with generic standard cells, memories and EDA design flows. It is compatible with the software and system interfaces of other well established MIPS32 cores 24K, 24KE and 34K™ processors.

Some the technical features of note are:

If you were an embedded systems software engineer, a very smart assistant who could check programs for you would be invaluable. Embedded systems are designed to perform a very specific and limited array of functions in systems ranging from consumer handheld devices to complex machine tools.

Because changing embedded software is relatively expensive, it is critical that the software is right the first time. A smart assistant would check your program to make sure that there were no errors. Klocwork, a Burlington, Massachusetts company, has developed static code analysis programs that are, in effect, that smart assistant.

Klocwork’s K7 is defined as providing static analysis because the code does not need to be run for the analysis to occur. Static analysis is a procedure for analyzing source code to gain an understanding of what the software does and to establish correctness criteria.

The programs can then check the software for defects and security vulnerabilities. This occurs at "Time Zero," directly as the developer is creating the code, before it is submitted for check-in or integration/system build and long before QA is engaged on the system. The static analysis program performs the function of a very skilled code review team.

Last week Intel and AMD reported their 1Q 2007 financial results which were widely covered. What is the significance of these results and what does it portend for the coming year and beyond?

A brief review

Intel reported corporate revenues of $8.852 B, down 9% q to q and down 1% y-over y. The MPU revenues were $6.0 B, down 8% q to q and down 4% y-over-y. The company attributed the drop to lower unit shipments, which was expected for the seasonality of the PC market. Intel noted that the ASPs for desktop and mobile were flat, but overall ASPs for servers were lower due to a mix of more low-cost single and dual processor systems.

Things were tougher at AMD. The company reported total revenues of $1.233 B down 30% q to q and 7% y-over-y. AMD now includes revenues from ATI which was acquired during 2006, so the drop for AMD’s MPU business is more significant. The computational products group (MPU and chipsets) had revenues of $918 million, compared to previous quarter of $1,486 (some ATI business) and $1,337 in 1Q06 prior to the ATI acquisition. Semico estimates that AMD’s MPU revenues in 1Q07 were about $750 million. This is a drop of 45% q-to-q and a drop of 44% y-over-y. AMD attributed this to both a drop in unit shipments and a drop in ASPs.

Semico Spin

With CAN, LIN and MOST already established, what would be the need for another connectivity solution? The answer is a need created by regional differences in automotive networking strategy. In Europe and Asia automotive manufacturers tend to distribute control of infotainment devices throughout the network, with each device controlling its own access to the bus. MOST is ideally suited for this approach.

In the United States automakers tend to concentrate functionality into the head-end unit of a vehicle’s infotainment networking system, an approach not particularly well suited for MOST. But, due to this approach, US automakers are faced with issues that are causing further integration to become increasingly complicated, more expensive, and inherently noisy. SMSC, a Hauppauge, New York company has introduced the eLITE connectivity solution, which provides a way for US automakers to design a simpler, more cost-effective infotainment system, which overcomes those problems and uses fewer components than current solutions such as an analog plus CAN network.

Semico Spin

The emerging Structured ASIC segment breathed new life into an ailing overall ASIC market. Structured ASICs allow previous users who have left overall ASIC market to once again contemplate using a Structured ASIC solution for their application.

The emergence of the Structured ASIC represents a new category of semiconductors for the industry. The Semiconductor Industry Association (SIA) does not currently have a category labeled “Structured ASIC.” Therefore, Semico Research Corporation has created a definition that captures most of the important features that can be used to define a Structured ASIC.

· Use of movable (re-usable) Intellectual Property (IP).

· Use of internal on-chip buses.