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As the rate of growth for smartphone sales slow, questions arise regarding the impact that slower growth will have throughout the semiconductor supply chain. Over the past decade, the 1 billion-plus smartphone market has driven the need for more advanced manufacturing process technologies, new input materials and the need for more fab capacity. It has even legitimized new players into the supply chain.

Does a slower growth rate mean a change is on the horizon? What portion of the growth is due to semiconductor content versus smartphone unit growth? Semico looked at the change in smartphone silicon content over the past 10 years and the impact on wafer demand.

Although there were smartphones well before the Apple iPhone, it was the iPhone, introduced in 2007, that set the smartphone on the path to the mass adoption that we see today. Between 2005 and 2010, smartphone sales grew at a compound annual growth rate of over 50%. In addition, over that time period, silicon content in a high-end phone doubled. The amount of silicon necessary to produce all the smartphones worldwide has grown from less than 1% of total wafers in 2005 up to over 18% of wafers this year.

The only semiconductor market segment that has not been taken over by the foundries and still remains dominated by IDMs is the memory sector. The memory market is the last bastion for true IDM manufacturers who must be savvy in the changing trends in end market applications, advanced technology development , and must still determine how much and when to invest in additional capacity.

With only four major players, the decision of when to add capacity should be more straightforward; instead, it’s just as challenging as ever. Large memory fabs are inherently more expensive and riskier than ever.

At their Winter Analyst Meeting on February 12th, Micron’s executives touched on a number of trends that memory manufacturers are addressing.

As we enter into the new year of 2016 with the worldwide economic cloud of uncertainty hovering like an unregistered drone, particularly in China, CES was still setting records. Bustling with over 170,000 attendees and over 3600 companies displaying their new products, the event was as hectic as ever.
There was a big showing from all the major automotive manufacturers and suppliers. Companies were showing off their new electric vehicles and virtual reality displays of autonomous driving concepts.

Innovations that I found notable revolved around new dashboard layouts and instrumentation displays including avionic heads-up displays that provide the driver with navigational information, safety, speed and personal communication information. In addition, several companies are introducing night-assisted vision systems. The goal of these systems is to provide information and access to accessories without having the driver take their eyes off the road. As well as providing a safer driving experience, these systems reduce drivers’ stress and improve the driving quality and experience.

Even though Tesla has located its battery manufacturing plant in Nevada, and they just recently announced a new vehicle, they were conspicuously absent at CES. . While Tesla is leading the industry in the vehicle electrification race, many of the big players are directly targeting them.

CES is the event that usually gets me energized about the upcoming year; however, this year I almost didn’t attend because I didn’t think there was going to be anything new that would shake up the industry. At the last minute I decided to put on my best walking shoes and fight the crowds. Unfortunately, I think my initial gut feeling was correct.

Sure, there were a lot of people waiting in lines to sit in the new self-driving and electric vehicles or eager to put on the new VR headsets, but there were still several things missing. IoT and power for our mobile electronics need a revolutionary innovation to attain the next level of ubiquitous technology.

First of all, I was disappointed to see so many booths still touting wireless charging solutions aka Powermat. I still have too many charging cables and every month that my phone or Fitbit device ages, the life of the battery charge declines. There were a number of people walking around with a cute, bright green bag that was plugging its ‘Big power, small cells’ product. I wasn’t sure what their product was, but I was definitely curious and feverishly looked for their booth. I was hoping they’d have a product that provided a breakthrough in battery technology or possibly an energy harvesting option. Unfortunately when I got close to their booth, I was handed the cute bag which included a USB charger that was powered by two rechargeable AA batteries. Really?

Whether it’s the Internet of Things, wearables, or industrial automation, many new devices and applications are portable and battery-operated. Wireless connectivity is required for connecting to the Internet. Today’s devices collect and transmit data from sensors, are always or almost always on and require power. The semiconductor industry has met the challenge to design devices for low power operation. Low-power microcontrollers and low-power RF are now available from many semiconductor vendors. But eventually batteries still run out of energy and have to be replaced or recharged.

The term energy harvesting, also known as power scavenging, is used to describe the creation of energy derived from a variety of external sources such as solar power, thermal energy, wind energy, kinetic energy or electromagnetic sources. Energy harvesters accumulate the wasted energy in a system, such as heat given off by motors or semiconductors, or the vibrations of motors or other moving objects. The basic technologies for generating energy are: mechanical vibration (kinetic energy), thermoelectric, solar (photovoltaic), and RF/Inductive.

If there is one constant in our mobile, connected society today, it is the continual demand for moving more data, more efficiently and at less cost.  This dynamic underscores virtually every technology and end market. It is a trend that is proving to be critical to the semiconductor industry as well as companies like Facebook and Google that participate in the efforts to create the standards necessary to deploy 400G data channels for data centers.
 
The high speed channel initiative is aimed at the data center. It is a certainty the high targeted speeds will allow more data to be moved more quickly into edge devices and eventually smart phones, tablets and other mobile devices. While the transition to these speeds by devices is still in the future, there is market pressure to increase the data communication capabilities of the SoCs in mobile systems.
 

In the past, integrated circuits, packages and boards were all designed independently and yet in most cases still managed to fit together with very few functional or technical problems. However recent advances in chip performance have changed this process dramatically. New designs, processes and materials have already been seen in packaging as high performance semiconductor chips need to carefully match the size, power and performance requirements of more demanding end applications. For optimal system performance, specific information related to material, speed and stability has created the need to improve information exchange and collaboration for successful board design. While collaboration is not new to the industry, we are now at a point where collaboration needs to be extended to all parts of the electronic ecosystem in order to maximize system performance while minimizing costs.

The vision of the Internet of Things places electronics in all aspects of our lives─from knowing what’s in our refrigerator to life-critical functions such as connected, implantable defibrillators. The potential of autonomous driving places our lives in the hands of sensors, processors and wireless communication that we have to assume collect accurate information, processes that information and reacts in real time. Semico has compiled a list of the top ten elements that must align in order for the IoT to come to fruition. Semico’s report on security started a groundswell of discussion and, more importantly, new solutions from chip vendors.

Semiconductor designers have been engrossed in developing solutions that deliver the right performance at the lowest cost while using the least amount of power. But there is another item to add to the list of essentials for IoT adopton. Making sure your customers know you, or more specifically your product specs, is even more important than ever. In the past five years, packaging has become a critical piece of a successful solution. System in Package, 3D chips, and 3D packaging have all been created to serve one or more angles of the power/performance/cost pyramid. What about the results once the chip is mounted onto a board with all its companion chips? How far should the chip manufacturer go in order to control and guarantee performance and reliability in their chips?

As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about.

Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that I think are driving growth and excitement at semiconductor equipment and material companies.

First, the major driver of equipment spending is changing from a focus on new greenfield fabs to the technology transitions that are and are not happening. Gary Dickerson, CEO of Applied Materials, clearly laid out the ‘inflections’. 3D NAND devices are a material enabling inflection and 10nm/7nm logic devices are driving a litho or patterning inflection. What does all this mean? The bottom line is more steps and more tools.

A recent article by Peter Clarke, EETimes, ‘TSMC Overtakes Intel in Chip Capex Ranking’ seemed to imply that a lower capital expenditure in 2015 was a bad sign. A growing capital expenditure budget does not always signal good times ahead just as a small capex does not mean disaster. Most companies are talking about the slowing or end of Moore’s law. Intel is one of the few companies that is back on Moore’s Law transistor density curve with their 14nm second generation Tri-Gate process. In fact, Intel has publicly stated that at 14nm they are ahead of Moore’s Law! Increased transistor density typically means smaller die sizes. All other variables being equal, this also translates to higher yields and less wafers required to meet market demand. A reduced capex is one of the benefits of improved efficiencies when a process obtains its sweet spot. Is it possible that others have to spend more in capex in anticipation of larger die sizes, lower yields and the need for more wafer throughput? A growing capex could mean expanding sales or the promise of a new market, but declining capex is not necessarily a bad omen. Remember when the industry experienced huge crashes because of the cycles that were caused by capex overspending? We haven’t experienced one of those in a few years, but I’m sure that can’t be erased from our memories yet.