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Whether it’s the Internet of Things, wearables, or industrial automation, many new devices and applications are portable and battery-operated. Wireless connectivity is required for connecting to the Internet. Today’s devices collect and transmit data from sensors, are always or almost always on and require power. The semiconductor industry has met the challenge to design devices for low power operation. Low-power microcontrollers and low-power RF are now available from many semiconductor vendors. But eventually batteries still run out of energy and have to be replaced or recharged.

The term energy harvesting, also known as power scavenging, is used to describe the creation of energy derived from a variety of external sources such as solar power, thermal energy, wind energy, kinetic energy or electromagnetic sources. Energy harvesters accumulate the wasted energy in a system, such as heat given off by motors or semiconductors, or the vibrations of motors or other moving objects. The basic technologies for generating energy are: mechanical vibration (kinetic energy), thermoelectric, solar (photovoltaic), and RF/Inductive.

If there is one constant in our mobile, connected society today, it is the continual demand for moving more data, more efficiently and at less cost.  This dynamic underscores virtually every technology and end market. It is a trend that is proving to be critical to the semiconductor industry as well as companies like Facebook and Google that participate in the efforts to create the standards necessary to deploy 400G data channels for data centers.
 
The high speed channel initiative is aimed at the data center. It is a certainty the high targeted speeds will allow more data to be moved more quickly into edge devices and eventually smart phones, tablets and other mobile devices. While the transition to these speeds by devices is still in the future, there is market pressure to increase the data communication capabilities of the SoCs in mobile systems.
 

In the past, integrated circuits, packages and boards were all designed independently and yet in most cases still managed to fit together with very few functional or technical problems. However recent advances in chip performance have changed this process dramatically. New designs, processes and materials have already been seen in packaging as high performance semiconductor chips need to carefully match the size, power and performance requirements of more demanding end applications. For optimal system performance, specific information related to material, speed and stability has created the need to improve information exchange and collaboration for successful board design. While collaboration is not new to the industry, we are now at a point where collaboration needs to be extended to all parts of the electronic ecosystem in order to maximize system performance while minimizing costs.

The vision of the Internet of Things places electronics in all aspects of our lives─from knowing what’s in our refrigerator to life-critical functions such as connected, implantable defibrillators. The potential of autonomous driving places our lives in the hands of sensors, processors and wireless communication that we have to assume collect accurate information, processes that information and reacts in real time. Semico has compiled a list of the top ten elements that must align in order for the IoT to come to fruition. Semico’s report on security started a groundswell of discussion and, more importantly, new solutions from chip vendors.

Semiconductor designers have been engrossed in developing solutions that deliver the right performance at the lowest cost while using the least amount of power. But there is another item to add to the list of essentials for IoT adopton. Making sure your customers know you, or more specifically your product specs, is even more important than ever. In the past five years, packaging has become a critical piece of a successful solution. System in Package, 3D chips, and 3D packaging have all been created to serve one or more angles of the power/performance/cost pyramid. What about the results once the chip is mounted onto a board with all its companion chips? How far should the chip manufacturer go in order to control and guarantee performance and reliability in their chips?

As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about.

Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that I think are driving growth and excitement at semiconductor equipment and material companies.

First, the major driver of equipment spending is changing from a focus on new greenfield fabs to the technology transitions that are and are not happening. Gary Dickerson, CEO of Applied Materials, clearly laid out the ‘inflections’. 3D NAND devices are a material enabling inflection and 10nm/7nm logic devices are driving a litho or patterning inflection. What does all this mean? The bottom line is more steps and more tools.

A recent article by Peter Clarke, EETimes, ‘TSMC Overtakes Intel in Chip Capex Ranking’ seemed to imply that a lower capital expenditure in 2015 was a bad sign. A growing capital expenditure budget does not always signal good times ahead just as a small capex does not mean disaster. Most companies are talking about the slowing or end of Moore’s law. Intel is one of the few companies that is back on Moore’s Law transistor density curve with their 14nm second generation Tri-Gate process. In fact, Intel has publicly stated that at 14nm they are ahead of Moore’s Law! Increased transistor density typically means smaller die sizes. All other variables being equal, this also translates to higher yields and less wafers required to meet market demand. A reduced capex is one of the benefits of improved efficiencies when a process obtains its sweet spot. Is it possible that others have to spend more in capex in anticipation of larger die sizes, lower yields and the need for more wafer throughput? A growing capex could mean expanding sales or the promise of a new market, but declining capex is not necessarily a bad omen. Remember when the industry experienced huge crashes because of the cycles that were caused by capex overspending? We haven’t experienced one of those in a few years, but I’m sure that can’t be erased from our memories yet.

Semiconductor companies are spending more than ever to stay competitive.  In 2015, the total amount spent is forecast to be $68.7 billion, up 9% from 2014’s $63.3 billion.  This breaks the previous record set in 2011 at $63.8 billion, as shown in the following graph. 

Total Semiconductor Capital Expenditures, 2009-2015

Source:  Semico Research Corp.

The Top 15

Accounting for almost 90% of the total spending are fifteen companies.  The top fifteen companies stayed the same from 2014 to 2015, but their order did change somewhat.  The top five spenders are no surprise, with Samsung in the top spot, followed by TSMC.  What is unusual is Intel slipping into the third position.  To round out the top five, GLOBALFOUNDRIES and Hynix switched places as the foundry expects to increase spending 22% this year versus Hynix’s 5% increase.  In the top fifteen, the company with the largest increase is Sony, with a 207% increase to almost US$2 billion.  The bulk of this increase is to expand image sensor production capacity, but some will also be spent on camera module production capacity, a relatively new market for Sony.  Sony’s dollar increase is second only to Samsung’s, but this is partly due to the decline in value of the yen.

On June 16, 2015 at the E3 show AMD rolled out its high end graphics GPU, Fiji, which features its High Bandwidth Memory (HBM) on its high end desktop graphics cards, the Radeon R9 300 series.

AMD’s top of the line GPU, Radeon Fury X has 4 GB of HBM delivering up to 512 Gbits/sec of memory bandwidth (increase of 63% over previous generation), with 4,096 stream processors and 64 compute units up to 1.05 GHz. The 28nm Fury X is liquid cooled. AMD also introduced air-cooled models, Fury with 56 compute units operating at 1 GHz and the R9 Fury Nano. All of these GPUs use HBM.

AMD is touting HBM for its improved performance and power consumption compared to GDDR5. The memory technology was developed by SK Hynix. The resulting solution offers three times the performance per watt with 94% less PCB area. This enables a smaller graphics card for the Fury nano card.

The enabling technology for HBM is the 2.5D packaging technology.  AMD and SK Hynix partnered to define and develop the first complete specification and prototype. The technology employs through silicon vias (TSVs) and micro-bumps to connect one stacked DRAM to the next. The stacked die also connect via TSV and micro-bumps to a logic die which provides the PHY interface to the GPU. Up to 4 stacks surround the GPU on an interposer.

NXP Key Partnerships for IoT

On May 5, 2015 NXP made two important announcements. NXP is partnering with Xiaomi to make smart home products.  In a separate announcement, Qualcomm will use NXP’s NFC and embedded secure element technology across the Snapdragon processor family.

Xiaomi is a fast growing Chinese consumer electronics firm. It is offering the Xiaomi Smart Home Suite which includes four wireless products: a motion sensor, door and window sensors, a wireless switching device for controlling appliances, and a multifunctional gateway that wirelessly links all the components together using ZigBee Wi-Fi interconnectivity.

Qualcomm and NXP are looking to expand NFC into new markets outside of smartphones, such as consumer electronics, automotive, home automation, smart appliances, personal computing and wearables.

Semico Spin

NXP has been deeply involved with the Internet of Things (IoT) since it first emerged. Partnering with Xiaomi will help develop the more effective Smart Home IoT.  Semico has forecasted that by 2020 there will be 36 billion connected devices worldwide. About half of these will be in smart home applications and the largest market will be in China. NXP is positioning itself for this trend.

First quarter 2015 is now history, and companies will soon be reporting their Q1 earnings.  Here at Semico we’ve checked the IPI Index against our forecast and year-to-date actuals to see if the industry outlook is on track for 2015.  Here’s the critical review.

First of all, Semico’s forecast for total semiconductor sales in 2015 is $378 billion, up nearly 9% over 2014.  Units will increase to 849 billion representing a 10.5% growth over 2014.  However, there is an upside to this forecast.  DRAM pricing is expected to remain strong as demand remains healthy and more complex fabrication processes reduce wafer output per fab line, limiting the potential for an over-capacity situation.  In addition, the largest memory supplier, Samsung, is slowing its DRAM ramp, i.e. pushing out capex for DRAM capacity.  The memory market has played a major role in the growth of semiconductor revenues over the past two years. 

On a quarterly basis, Q1 2015 is expected to result in a sequential decline of 2.1% compared to Q4 2014 and a 5% year-over-year increase compared to Q1 2014. 

Quarterly Semiconductor Revenues and Units

(In Millions of US Dollars and Units)

Source:  SIA/WSTS and Semico Research Corp.