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There are two common terms when describing sensors.  One is “degree of freedom” (DOF) and the other is “axis.”   They're often used synonymously, originating when accelerometers, vibration sensors and tilt sensors were first used in industrial and military applications for monitoring movement, such as a robotic arm or a space craft.  Yet, they don't mean the same thing.  Technically, a DoF is a parameter that determines the state of a physical system and it takes six numbers to characterize a movement. 

So, six degrees of freedom indicates the sensors track up and down, side to side, forward and backward, pitch, roll, and yaw.  A device can really only have a maximum of 6 DOF, because there are only 6 degrees of freedom in a 3D space.  When a company claims a higher DOF (like 9), they’re really implying a higher degree of accuracy within the linear and angular 3D space.

Which means the more accurate term when discussing sensors is "axis."

The axis term refers to the X, Y, and Z axis, so a 1-axis sensor most likely goes up and down on a Y axis or side to side on a X axis.  A 3-axis sensor would track on all three axes.  A sensor platform that is said to have 9, 10, or 12-axes indicates that it tracks multiple data points along the X, Y, and Z axes. The number of axes a device is said to have can be as high as the developer wants - as long as each additional axis tracks data along one of the x, y, or z axes, it can be added on to the total. 

About a year ago Sand9 was a startup just coming out of stealth mode.  Little was known other than it had innovative MEMS timing technology.  The company is starting to roll out product to market.  On September 3, 2013 Sand9 announced the TM061 and TM361 touted as the “First precision MEMS Timing products for the Internet of Things and Mobile.”  On November 18, 2013 the company announced the TM651 to meet the rigorous requirements for precision timing in communications infrastructure, industrial and military applications.

Sand9 is using a platform strategy for its product lines.  The two platforms are MR (MEMS Resonator) and TSMR(Temperature Sensing MEMS Resonator).  The first device offered for MR is the TM061.  The first one for TSMR is the TM361.

Sand9 implements a piezoelectric MEMS technology.  Traditional MEMS use electrostatic technology which has issues with performance and low power.  According to the company, its piezoelectric resonator architecture has higher performance and lower power.  The temperature detection and compensation in the TSMR is achieved by sandwiching a layer of Si (silicon) between two layers of SiO2 (silicon dioxide).  As the temperature increases SiO2 stiffens while Si softens.  The two layers compensate each other.

Microchip has announced an addition to its 32-bit MCU line of PIC32 called the PIC32MZ Embedded Connectivity (EC) family.  The PIC32 is based on the MIPS architecture.  The new PIC32MZ is Microchip’s first MCU to feature Imagination’s MIPS microAptiv™ core.

The microAptiv core adds 159 new DSP instructions that enable the execution of DSP algorithms at up to 75% fewer cycles than the PIC32MX families.  Microchip has tripled the performance over its previous generation reaching 330 DMIPS.  The microMIPS instruction set also enables improved code density for the PIC32MZ.

Microchip has integrated a large number of peripherals, mostly to support high speed connectivity: Hi-Speed USB, 10/100 Ethernet MAC, 2 CAN 2.0b modules, 6 UART, 6 SPI / I²S, 5 I²C™ and SQI (Serial Quad Interface).  The SQI supports high-speed interface to external Flash.  Integrated onto the PIC32MZ is up to 2MB of Live-Update Flash.  This is the Flash technology Microchip acquired with SST.

The PIC32MZ targets a broad range of applications which include automation (factory, building and home), consumer audio, automotive, security, power meters and cloud computing. 

Healthcare has been changing in big ways.  These days, a good system can monitor a patient and then use that data to enact behavioral change for an entire society.  Changing society for the better is basically the end goal of Big Data.  

Big Data in healthcare means mining personal data that can be applied either to personal care or combined with large demographic segments to spot trends and improve care to either cure or manage disease and sickness or to change behavior in a positive way.  

For example, technology like Dexcom’s glucose monitor, watches blood sugar levels every five minutes for five days, and is approved by the FDA.  Since controlling sugar is so important, someone who is diabetic can now send complete data to their doctor.  This is something patients have never before been able to do.  This constant stream of data is “Big Data” in that, even if there isn’t a cure, disease and sickness can still be managed by understanding our smallest reactions to daily stimulus.  

This becomes predictive modeling, which means decreased health costs, and implies an upcoming data deluge.  It is possible to get a trillion GB of data for each individual.  The amount can be astronomical, and apps will need to sift through the data to get to the relevant and actionable data (Market Opportunity for new Tech).

John Koeter of Synopsys spoke at the Semico Impact Conference: Focus on the IP Ecosystem (November 6, 2013) about a new class of data center SoCs. Koeter is vice president of the Marketing Solutions Group at Synopsys. In this capacity he is responsible for the marketing of Synopsys' DesignWare® Intellectual Property (IP), Professional Services and System-Level Design products.

Koeter noted the trend of increasing internet traffic which is being driven by the mobile market. Globally, peak Internet traffic is expected to grow 3.5x from 2012 to 2017, a 29% CAGR. This will impact the IP world, as semiconductors are expected to meet the changing needs of the data centers. He foresees a major sea change in the data center. The trends are for software defined networks (SDN) and low power micro servers. Also, there will be improvements in the cost/performance ratio achieved through application acceleration with PCIe SSDs.

According to Koeter SDN will reach 35% penetration of the Ethernet switching by 2016. Data centers are moving away from proprietary solutions that are vendor specific. For semiconductor companies this represents $3.7 billion market for SDN and network infrastructure. New architectures are emerging to meet the needs of the data centers. The new semiconductor devices will be SDN-enabled switch ASSPs and SDN-enabled communication processors. Highly integrated processors for new micro servers which are focused on reducing power are necessary.

I had a very interesting discussion with Sundar Iyer, CEO of Memoir Systems, during a briefing they gave Semico on their just-released Pattern Aware Memory IP technology.

To briefly restate their announcement: Memoir has researched the different interactions between processors and memory in high-performance datacom systems and found that certain operations recur fairly often.  These operations roughly fall into four groupings: Counter Memory, Sequential Memory, Allocation Memory and Update Memory.  There are probably many more than these types, but Memoir is starting with these operations to begin with.

Memoir Systems is a 3^rd party memory IP company and, as such, devotes its time to developing and introducing embedded memory IP to the market. In the case of this new product announcement, the memory IP they are introducing is tailored around the four functions mentioned above. In other words, their memory IP is now configured to better support these specific operations at the memory level and not through software at the processor level in the system. This has large implications for system performance and throughput.

At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fellow; and Warren Savage, President and CEO, IPextreme.

Tirupattur skillfully pulled both humorous and discriminating observations from the foundry perspective, the EDA perspective and both a large and small IP vendor.
The topic of the panel was the high cost and risk of integrating IP in today’s semiconductor product development. There’s a massive risk of product failure from choosing the wrong IP, the wrong supplier, the wrong fab, or the wrong process. A misstep means jobs could be on the line. Today, complex SoCs are not comprised of just one or two IP blocks, it’s a battalion of IP coming from a variety of sources. Dan Kochpatcharin of TSMC noted that at the 20nm node an average design has 12 unique IP blocks. That compares to an average of only eight at the 28nm node.

The System-on-Chip (SoC) market has been successful because of the increasing use of 3rd Party Semiconductor Intellectual Property (SIP). SoC designers now look to move up a layer of abstraction to design with system level functionality in order to reduce the effort and cost associated with complex SoC designs. By doing so, SoC designers can add higher levels of system functionality and cutting-edge feature sets without needing to design these functions at the absolute lowest level of complexity.

The IP subsystem is a methodology designers are employing to infuse the right level of complexity and functionality to meet rapidly changing market requirements without experiencing a corresponding increase in design costs or design cycle time.
The market entry by Cadence, Synopsys, Sonics and Analog Bits over the past 12+ months marked a turning point in the IP subsystem era. Semico expects to see a competitive market for 3rd party IP subsystems in the follow areas:
• Computing subsystems
• Memory subsystems
• Video subsystems
• Communication subsystems
• Multi Media subsystems
• Storage subsystems
• Audio subsystems
• Security subsystems
• System Resource Management subsystems

Electronic devices have evolved from cyclical killer applications to everyday ‘must-have’ tools.  Smartphones and tablets are a couple of these ‘must-have’ devices and are already making possible new world applications.  Many of these new world applications, including the Internet of Things and mobile health, will be pervasive and promise high semiconductor unit volumes.  Semico has identified 70 appliances in the average home that can become part of the Internet of Things.  Before we experience the hockey-stick growth in these markets there are a few hurdles to overcome: 

Last week there were reports in the media that users were complaining of off-the-mark readings from the Apple iPhone 5S compass.  Compared to the previous iPhone 5, Apple’s native compass app is displaying discrepancies an average of 8 to 10 degrees with both devices running iOS7.

This has caused “wonky” game experiences such as in driving and physics-based games that rely on tilting the screen for in-game motion.

This has brought into question whether or not this is a hardware malfunction with the motion sensors or some other chip.  There are several teardowns available online.  An examination of the bill of materials shows that the iPhone 5S has:

• Gyro: STmicro
• eCompass (magnetometer): AKM
• Accelerometer: Bosch Sensortec
• NXP LPC18

The NXP LPC18 is an ARM Cortex-M3 MCU.  It is a coprocessor for the Apple A7 Apps Processor.  This MCU is the sensor hub controller of the iPhone 5S.  It has been referenced as the M7.

The first things that came to my mind as to the cause of the problem: