Impact Of Rising SoC Design Costs On Innovation

(Originally published at semiengineering.com)

If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design costs), the overall impact can be similar. In this case, the number of design starts is impacted by the climate of rising design costs.

Following are a few of Semico’s findings.

1. The total number of Advanced Performance Multicore 1st time SoC design starts has been roughly flat to only slightly up over the past 5 years
2. Value Multicore SoC design starts show a higher growth rate over this time period
3. In the next five years, the majority of growth will be in 1sttime Basic SoC design starts primarily focused on IoT applications
4. Derivative designs of these 1st time efforts continue to rise, outpacing the 1st time efforts themselves by a wide margin
5. Design starts at the advanced nodes will continue to occur in order for the market leaders to create the functionality needed for the most cutting edge application solutions
6. The time needed for the second wave of designs to migrate to the advanced nodes has lengthened as many companies cannot afford the design costs at the most advanced geometries
7. Overall, the SoC design landscape is healthy, but the environment is changing as companies adjust to the new design cost structures

As SoC design costs increase at each succeeding process node there could be several impacts to the market.

• The pace and number of the most complex designs at the advanced nodes (the ‘bleeding edge’) will continue to be flat to slightly up, over the next five years, i.e. not be much different than we have previously seen.
• The market leaders will continue to aggressively rollout new designs in order to maintain their market leadership.
• There is always a gap between when a new process geometry is introduced by the leading companies doing the most complex designs and the next group of companies doing less complex designs but still needing the features or attributes that the new process geometry offers.

Many of these statements are not new to most people. Design costs have been rising steadily since the 40nm node, but it is the acceleration in design costs at 7nm and 5nm that are the most worrisome to the industry. Mobile and Wireless, Artificial Intelligence, Deep Learning / Big Data, ADAS and Embedded Vision will require high complexity silicon and will utilize the advanced nodes. Semico believes these applications will push the market leaders to utilize the ‘bleeding edge’ process technology.

But Semico is already observing a shift in the companies that participate in the second wave of designs. One of the major sources of innovation is found in the designs accomplished by the second wave of products that are introduced by companies that trail the bleeding edge. The functionality and rich feature sets that are found in advanced designs have provided a path for pioneering but less complex designs two or three years later. Once these designs have been proven and the cost structure to create them has become more moderated, other designers jump on the bandwagon. This has always been the case in the semiconductor industry and is not a new trend. However, Semico has observed a lengthening of the time interval between the initial entrants and when the 2nd wave companies are able to deliver their solutions.

Semico is forecasting that the Compound Annual Growth Rate (CAGR) for designs of Advanced Performance Multicore SoCs will be in the 3.2% range over the next 5 years. These are the design starts that will mostly be aimed at the new applications entering the market.

While the far future is somewhat cloudy, the near term still shows reasonable growth for the nodes down to 10nm. Beyond 10nm, design starts are going to be more constrained by rising design costs. Although Semico does not see the total number of designs that migrate to the new nodes being appreciably different than in previous process geometry transitions, we do believe the time frame for such transitions by the majority of companies doing designs at these levels will be somewhat longer.

These findings will be detailed in two new reports on the ASIC Design Landscape: SC105-17 and SC106-17. Semico would like to hear your opinion on this very important issue.

Do you think that the accelerated increase in design costs associated with 7nm and 5nm designs, will lengthen the time interval between the initial users of these geometries and the 2nd wave of product designs?

We welcome your comments. If you’re interested in more information on the ASIC Design reports, please contact at rickv@semico.com or visit us at https://semico.com.