ASIC Design Starts: Changes in Industry Dynamics

The current global slowdown in economic conditions is having an adverse impact on the design start universe for ASICs. This can be seen in the slowing of design start activity towards the end of 2008 and forecast for all of 2009. Semico believes 2010 will see a recovery in design activity back to more historical norms. An in-depth perspective on these impacts is provided by showing a comparison between design starts for SoCs and all other types of ASICs and the continuing increase in SoC design costs.

The report uses the data outlined in SC104-09 by individual end application and aggregates this data by the major categories of Computer, Communications, Consumer, Transportation and Industrial. This data if further analyzed to provide insight into how the ASIC Design Start landscape is changing in response to market and economic conditions.

The report provides historical data and a forecast for ASIC design starts for 2007 – 2012 by end application. The ASIC design start data is further analyzed to show changes in design for each device type like Analog, Mixed Signal, Gate Array, PLD, FPGA, Performance SoC, Value SoC and Structured ASIC. This analysis is continued to show the design start data by product type by process geometry, by gate count and by region for both the number of design starts and the unit shipments for each product type in each category.

The report is 80 pages in length and consists of 55 tables and 58 charts. It is recommended that report SC104-09 also be considered since this report provides ASIC Design start data by 66 individual end applications for the Computer, Communications, Consumer, Transportation and Industrial markets.