The GigaChip Interface: A Network Processing Memory Access Time Solution

In an a May 2, 2011 presentation at the Semico Summit, Mr. Len Perham CEO, MoSys, Inc. discussed looming problems in the processing of Internet traffic and offered a solution. According to Mr. Perham, Internet traffic will increase exponentially over the next three years, driven by applications such as video streaming, IPTV, P2P, cloud computing, social networking and VoIP + video.  Today’s traffic routing methods will not be able to keep up with that growth, and memory is the bottleneck. 

The problem is that today’s 40Gbps and 100Gbps packet processor line cards address memory on parallel connections, which will not be adequate at faster speeds beyond 100Gbps.  Routing data at those speeds will require a serial connection to the memory, not a parallel connection. MoSys has developed the GigaChip™ Interface, which is now an open standard supported by the GigaChip Alliance. 

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance.   It provides a fundamental performance breakthrough similar to the breakthrough achieved by DDR (Double Data Rate) DRAM.   The GigaChip Interface, using differential SerDes technology, is the next breakthrough in network processor to memory connections.  It allows a multiple-processor network processor to address multi-bank, multi-partitioned memory, so that each processor has access to memory without waiting.

Mr. Perham also discussed the advantages offered by 1T-SRAM®, a memory architecture originally invented by MoSys .  1T-SRAM has the approximately the same latency as the standard  6T SRAM cell generally used in today’s high speed applications, but because it has one transistor per cell as opposed to six per cell for standard SRAM’s the ultimate memory area is approximately one third that of the standard SRAM.     

The MoSys Bandwidth Engine® IC Roadmap anticipates a BE-3, utilizing the 1T-SRAM architecture, which will have a memory capacity of 1Gb and an access speed of 7.4Gbs. Memory access has been a continuing problem for network processors over the past several years as Web traffic has increased, requiring ever faster processing speed.  Various schemes have been used to speed up access times on parallel interfaces.  Now, parallel access appears to have run out of steam.  Serial access, using the GigaChip standard shows promise as a solution going forward.  The 1T SRAM may have found a home in this application, an applications that needs the 1T SRAM’s unique combination of access speed, high density and low power.

Morry Marshall VP Strategic Technologies