Semico_Admin's blog

I guess I’m a gearhead. I like double overhead camshafts, six speed transmissions and small-displacement, high revving engines that make lots of noise. I like fast cars with great handling. I’m having trouble adjusting to hybrids and even more trouble adjusting to plug-in electric cars that need to have electronically generated noise added to alert pedestrians. Low-performance econo-slugs aren’t interesting to me.

A colleague, not a car guy, suggested that electric cars would never sell until they raced at the Daytona 500 – maybe a NASCAR car in electric blue. That hasn’t happened yet, but electric cars are setting speed records.

The Buckeye Bullet (version 2.5), an electric car designed and built by students at Ohio State University’s Center for Auto Research, recently set an international record for electric cars, an average of 307.7 miles per hour in back-to-back runs on Utah’s Bonneville Salt Flats. That may seem slow, but the wheel-driven land speed record car needed a 3,750hp turboshaft engine to go 470.4 mph.

The Buckeye Bullet was sponsored by Venturi, a French electric vehicle company; and used lithium ion batteries designed by A123 Systems of Watertown, Mass. Both are involved in the production of electric or hybrid passenger cars.

On January 18, 2011 CEITEC S.A., a semiconductor manufacturer in Porto Alegre, Brazil, announced the successful completion of a 12 month field trial of an RFID chip that can be implanted in cattle for positive identification. This application is important for Brazil. Beef is one of Brazil’s largest exports. The RFID chip will allow beef to continue to be shipped to Europe and Japan in the event of a mad cow disease scare in South America; because the origin and movements of cattle can be tracked, from ranch to market, providing proof that the beef is not from a suspect herd or area. The rest of the world should take notice. This is a Brazilian semiconductor, designed and fabricated in Brazil. What do you think about when you think of Brazil: inflation, F1 racing drivers, soccer, something else? Think again! Brazil is a major market. It is a country of more than 200 million people, the fifth largest country in the world. It has a stable, democratic government, and inflation has been brought under control. It is one of the BRIC countries (Brazil, Russia, India China), identified as developing countries with high growth rates and the potential to become among the world’s dominant economies in the future. Although Brazil’s GDP growth dropped in 2009, along with the rest of the world, its GDP has been growing at rates exceeding 5% annually. CEITEC S.A. is a startup IC company partially funded by the Brazilian government.

The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures the entire electronics market has undergone, it is the 3rd Party SIP market.

Most of these evolutionary forces are driven by the need to integrate more functionality in fewer devices at the system level and in ever-smaller footprints. One method to accomplish this is through the use of 3rd Party SIP. However as design costs and time to market pressures mount on SoC designers, it is becoming more and more difficult for these designers to craft their silicon solutions in a timely and cost effective manner.

Enter the IP Subsystem, organized by system-level functionality and around its own internal interconnects, as one contiguous block accompanied by its own testbench of verification IP and small to large amount of applications software.

The IP Subsystem is the method SoC designers will employ to infuse the right level of complexity and functionality into their silicon solutions to meet quickly changing market requirements without experiencing a corresponding increase in design costs or design cycle time. Larger parts of the design can be dealt with at one time opening the door for the applications software to be written in parallel for each subsystem used in the design.

The 2010 Flash Memory Summit wrapped up last week in Santa Clara, CA.  Three days of breakout sessions, technical discussions, tutorials, flash exhibits and keynote speakers provided attendees with ample opportunity to gather intelligence related to the future of flash memory architectures.

Inevitably, most who attended are likely to come to the same conclusion; Denali’s reputation for throwing great parties is well deserved.  Wait, that’s not what I meant to write.  What I meant to write was… the gigabyte rules.  While there were numerous relevant points discussed over the three day event, let’s focus momentarily on a story told by Ed Doller, VP Micron Technology, which best illustrates both the state and future of flash memory.

Ed spoke on Thursday, August 19 to a packed theater on the topic of “Flash Memory—The New Technology Driver”.  He cited a number of technology advances over the last several years including the rapid adoption of social networking sites like Facebook and Twitter.  While it’s easy for many within the industry to focus on delivering improved performance by enhancing a number of technical capabilities consumers desire, it all boils down to memory.

On Thursday, the 10th of June, Synopsys announced its intention to acquire Virage Logic for $315M ($289M after accounting for cash in Virage’s possession). The acquisition is expected to close around late October of this year.

This transaction will provide Synopsys with many diverse types of SIP such as Memory cells (both volatile and non volatile), Memory compilers, Memory controllers, Interface I/Os, the ARC CPU cores along with Audio and Video IP blocks, some limited ‘Mega-Blocks (SIP that merges the ARC CPU cores with Audio / Video IP), basic Interconnect SIP, some basic Analog and Mixed Signal functionality, Standard Cell libraries, Communications IP, and a host of basic logic functions. In essence, Synopsys will now possess most of the elements needed to create their own SIP Sub Systems as complete products to be offered to the market at large. While Synopsys has not signaled their intent to create such SIP Sub Systems directly, they have hinted this is the direction in which they will go and it is a logical step for them to do so. Bringing more value to their customers – through offering better performing, more highly converged products as SIP Sub Systems, will ultimately bring more value to Synopsys.

Intel gave an in-depth look at their Moorestown platform aimed at Smartphone designs to selected analysts on Monday the 4th of May. My colleague, Tony Massimini, is dealing with the particulars of Moorestown as a platform in a separate Semico Spin article. My article is going to deal with looking at the Moorestown architecture and its implications for SoC designs going forward.

One of the very interesting features of the Moorestown platform is in how it deals with power consumption in Smartphone applications. Intel is competing with ARM-based SoC solutions in this market and is being measured over several parameters that are important to Smartphone designers – not the least of which is power consumption. Intel has done a very good job in abstracting the X86 architecture and instruction set into its Atom CPU core, which is used in the Moorestown platform. This has also meant reducing the power consumption of an Intel-based processor and chip set. However, Intel is thinking a little bit beyond simple comparisons between one SoC and another to comparing the power consumption figures of one Smartphone platform to another. True, this is being done to put Intel in the most favorable light possible, but the idea does have some merit since consumers do not care about the specs of individual parts but rather about metrics that are meaningful to them like ‘talk time’, ‘standby time’ and total battery life.

According to Atheros Communications, IEEE’s P1901 powerline networking draft standard is on schedule to be ratified early this fall. Semico believes that this will spur a high growth phase for powerline networking.

A powerline network makes a lot of sense. It uses the electrical wiring in a home to connect PCs, home entertainment systems, TVs and other electrical or CE devices. The wiring is already there. There is no need to thread expensive new wiring through the walls or attic of a home. Connections are available wherever there is an electrical outlet, and it’s as easy as plugging a module into the outlet. Connections are easy, truly plug and play. So why isn’t it more pervasive?

One obstacle has been the lack of a widely accepted powerline networking standard issued by an internationally recognized organization. The first powerline networking standards were for home automation and did not have enough bandwidth for multimedia. Others that followed did have the bandwidth; but, as usual in the electronics industry, groups of companies established separate standards to vie for market share for their products. The most widely used standard has been HomePlug AV, issued by HomePlug, an alliance of networking industry leaders. More than 40 million HomePlug AV devices have shipped worldwide.

Where is the next semiconductor marketing opportunity?  Maybe it’s not a specific application, geographic region or country but an overlooked portion of the world’s population. 

In the developed world, we drive upscale cars, travel around the world and want to be connected 24/7.   We understand immediately the appeal of stability control, GPS navigation systems, powerful laptops, smart phones, Wi-Fi and 4G. Our expectations taint our evaluation of potential markets. 

The annual GDP per person in developed countries is more than $25,000.   In the US, as an example, it’s nearly $50,000.   But, the annual GDP per person for more than 80% of the world’s population is less than $10,000 per year.   For nearly 40% of the world’s population it’s less than $2,000 per year. For nearly 15% it's less than $1,000. 

Because not everyone is a wage earner, average earnings are less than the annual GDP per person.  If the annual GDP per person is $10,000, for example, the average annual earnings may be as low as $5,000 to $6,000.  Let’s be generous and say it’s $6,000.  That doesn’t correspond directly to an annual salary of $6,000 in the US.   These are subsistence economies.  People raise most of their own food, and a lot of what they need is obtained by barter.  Still, there is far less than $6,000 per year available for discretionary spending in a country with an annual GDP per person of $10,000 and even less in countries with a lower annual GDP per person. 

There has been intense press coverage of the Apple iPad, but not much about the iPad’s impact on the semiconductor industry. That issue is addressed in a new Semico Research Corp. Market Brief, “Apple iPad: Where Will the Chips Fall?”

An important question is whether or not a new market is being created.  There have been numerous attempts at tablet PCs, beginning with the Apple Newton and the AT&T Hobbit. Until now, all have failed; but the situation has changed.  Three applications have emerged since previous tablet PC attempts: Internet access, social networking and electronic books.  These are ideal applications for a tablet PC.  Will they be enough for the iPad to succeed where others have failed? 

There have been a wide range of analysts’ forecasts for iPad shipments, some as high as ten million units for the first year. Semico takes a more realistic view, forecasting total shipment of 1.8 million tablet PC shipments in calendar year 2010.  Higher volumes will follow.  This time around, tablet PCs will succeed.

The iPad uses a proprietary processor and operating system.  Is this the beginning of a trend away from existing MPU architectures?  Will other tablet, netbook, notebook or desktop PC companies follow Apple’s lead?  What will that do to the MPU market?

On March 23rd, 2010, the Silicon-On-Insulator Consortium (SOIC) announced a new program geared towards creating an ecosystem for Semiconductor Intellectual Property (SIP) around SOI wafers. The initial members of the IP ecosystem are IBM, ARM, Ltd., and Cadence Design Systems, Inc. additional members include Synopsys, Inc. and Boeing, Corp. The idea behind this announcement is to establish an IP ecosystem to provide the building blocks essential to crafting System-on-a-Chip (SoC) designs and to establish a list of EDA vendors that have tool sets to facilitate these designs on SOI wafers. Currently, the IP is only for IBM’s 45nm SOI foundry process, but will broaden out to include 65nm and 28nm process geometries and presumably other foundries’ processes as well.

The addition of other process geometries and other foundries’ processes will further increase interest in doing designs on SOI wafers. The entire process of having major players in the semiconductor, IP and EDA markets come together to collaborate on developing this ecosystem validates the proposition that SOI can bring greater long term benefits than by just continuing to use bulk CMOS