Synopsys to Acquire Virage Logic

On Thursday, the 10th of June, Synopsys announced its intention to acquire Virage Logic for $315M ($289M after accounting for cash in Virage’s possession). The acquisition is expected to close around late October of this year.

This transaction will provide Synopsys with many diverse types of SIP such as Memory cells (both volatile and non volatile), Memory compilers, Memory controllers, Interface I/Os, the ARC CPU cores along with Audio and Video IP blocks, some limited ‘Mega-Blocks (SIP that merges the ARC CPU cores with Audio / Video IP), basic Interconnect SIP, some basic Analog and Mixed Signal functionality, Standard Cell libraries, Communications IP, and a host of basic logic functions. In essence, Synopsys will now possess most of the elements needed to create their own SIP Sub Systems as complete products to be offered to the market at large. While Synopsys has not signaled their intent to create such SIP Sub Systems directly, they have hinted this is the direction in which they will go and it is a logical step for them to do so. Bringing more value to their customers – through offering better performing, more highly converged products as SIP Sub Systems, will ultimately bring more value to Synopsys.

This acquisition comes on the heels of the Cadence acquisition of Denali which came after the initial publishing of the Cadence EDA360 white paper. It would seem that Synopsys felt the need to counter the Cadence move with one of their own, but is it really that simple?

All of the above is pretty straightforward in itself, but what are the real implications for the SoC market, the SIP market and the EDA market going forward? The following ideas will try to put these events in perspective.

Without a doubt, the landscape in the three markets mentioned above is changing driven by the increasing cost of SoC design, rising SoC complexity and the escalating cost and importance of applications software to run on the SoC once it is done. An inability to manage all these elements successfully calls into question whether or not the company producing the SoC will enjoy the right level of profitability on the silicon to make the effort worthwhile in the first place. Conversely, an ability to manage all these elements of the design process would give a company possessing them a decided leg up in the marketplace. Based on the tenets put forth in the EDA360 white paper, and the recent actions by Cadence and Synopsys, the industry is moving in the direction of putting in place changes to the SoC design methodology that solve, or at least mitigate, some of these issues. This will be done by offering more highly integrated solutions that increase the performance of the end silicon and that offer a way to manage the convergence of the  functions required in contemporary system design today.

Because at the end of the day it is no longer so much all about the silicon itself, or even about the process people take to design the silicon. It is about approaching the entire process of creating the silicon in such a way that the final system implementation is made better, easier, higher-performing and more cost effective.

One can also interpret these events from a different direction.

There are over 400 SIP companies in the market today, half of which have revenues of less that $1M. Many of them are good companies with good products, but are limited in scope due to their small size. With the recent acquisitions of Denali and Virage, the wave of consolidation that has been predicted for the last several years would seem to be underway and that these are only the opening moves in that process. However, one can look at this in another way.

An alternative view instead could be that the days of being a SIP vendor with ‘me-too’ products is coming to a close. The market can no longer reward products that do not bring value through innovation to it. Just by having SIP the success of a company is no longer guaranteed, as it was ten years ago when the market was buzzing about that very exotic animal: 3rd Party Semiconductor Intellectual Property. In today’s market environment, not only must the SIP products be of high quality and performance, they must also integrate more functions that had previously been individual discrete blocks and they must provide value to the customer. In a word, they must be innovative.

The words, “Necessity is the mother of invention”, have never been truer than in today’s environment.

Semico believes that, given the right prompting by the market, we could see a push towards products that lend themselves to architecting better system solutions instead of only addressing the implementation of better silicon solutions. While no one would argue that better silicon solutions are not desirable, they do not solve all the problems facing systems’ companies today. How does one get a handle on the massive software development efforts required to pump out the next killer Smart Phone or Netbook? How does one extend the battery life of a product that has an increasing silicon content in it to provide the new features and functions consumers want?

One way to do this is to create products that offer solutions to the issues facing designers outlined above that either directly address the system integration issues these questions pose or to create an ecosystem and environment that lends itself directly to enabling the SoC designer to solve these issues him / herself.

SIP Sub Systems, if architected the right way, can provide some of the solution. A comprehensive design environment that includes methods to address SIP integration, applications software creation tuned to the SIP Sub System and the SoC silicon and method of tying testbenches and verification information to the SIP Sub Systems as a complete, deliverable all-in-one package can empower the final system solution.

Semico believes that the recent moves by Cadence and Synopsys are merely steps along this path and that new EDA-flavored products that include in-depth management of the SIP integration and applications software creation functions are on the horizon.

However, just like no one has a corner on the market for good ideas, no one company will be able to produce all the system level solutions needed to enable the next ‘gotta-have’ consumer product. It will take a concerted effort by many companies at many levels to create the right products to do this.

As far as the 3rd Party SIP market is concerned, Semico believes this creates a place at the table for smaller companies that have innovative products and solutions to continue to participate in the market going forward. There will continue to be consolidation, but there will also be new companies emerging around these innovate solutions to take the place of those who are acquired or who exit the market altogether. This should be viewed as a process and not as an endgame. This is especially true in light of the looming wholesale deployment of nanotechnology and meta materials into the semiconductor design and manufacturing flow. These will be disruptive technologies that will create even more opportunities for innovative companies and products.

One thing is certain:

DAC 2010 is going to be very interesting this year!