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IP Availability for SOI Designs to Boost SOI Production

On March 23rd, 2010, the Silicon-On-Insulator Consortium (SOIC) announced a new program geared towards creating an ecosystem for Semiconductor Intellectual Property (SIP) around SOI wafers. The initial members of the IP ecosystem are IBM, ARM, Ltd., and Cadence Design Systems, Inc. additional members include Synopsys, Inc. and Boeing, Corp. The idea behind this announcement is to establish an IP ecosystem to provide the building blocks essential to crafting System-on-a-Chip (SoC) designs and to establish a list of EDA vendors that have tool sets to facilitate these designs on SOI wafers. Currently, the IP is only for IBM’s 45nm SOI foundry process, but will broaden out to include 65nm and 28nm process geometries and presumably other foundries’ processes as well.

The addition of other process geometries and other foundries’ processes will further increase interest in doing designs on SOI wafers. The entire process of having major players in the semiconductor, IP and EDA markets come together to collaborate on developing this ecosystem validates the proposition that SOI can bring greater long term benefits than by just continuing to use bulk CMOS

In general, creating a comprehensive ecosystem around IP aimed at use in SOI designs will be beneficial to the industry in the long run. However, in this case, the specific value of these announcements is the willingness of manufacturers and EDA companies to step up and go to bat for SOI regarding the cost benefits of using SOI over bulk CMOS. This seems like it could have the biggest short and long term benefit to the SOI camp. Just educating people on the fact that when you take into consideration the total cost to create designs on SOI, the increase in performance and decrease in power consumption, and not focus on just the actual wafer costs, the overall, long term benefits will be much greater. This will jump start people going in the SOI direction more than by just having a complete IP ecosystem available. The ecosystem will help the people who are already predisposed to favor SOI wafer for their next design. The education of those not predisposed towards using SOI today will have a larger impact since there are many more companies in this last group. Just getting some of these ‘hold-outs’ into the SOI camp will have a bigger effect over the long term.

Richard Wawrzyniak
Senior Analyst ASIc/SOC

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