Sonics and the Semico IP Ecosystem Conference

Grant Pierce, Chief Executive Officer, Sonics, Inc., gave a keynote presentation at the Semico Impact Conference: Focus on the IP Ecosystem on May 16, 2012.  His presentation that looked at the rise of cloud computing and its impact on the SoC market. Today, consumers expect connectivity ‘Anytime, Anywhere’ and can mostly get what they want over the various networks in the market today. However, as more of that connectivity functionality that resides in the ‘cloud’, increases in device performance are necessary to keep pace with the rich features that reside in the cloud. This puts pressure on SoC design and SoC architectures. Cloud-scale devices are driving SoC complexity due to the following market demands.

• Relentless push for higher quality user experience – at minimum system cost
• Feature convergence – video, voice, data and audio in every consumer device
• Critical demand for multi-GHz performance
• Most mobile devices today run user applications
• These applications need 1-3GHz multicore CPUs. 1-2 cores today, 3-4 cores tomorrow
• 100+ GFLOP multicore GPUs
• 15 – 50 GB/sec DRAM

Given these device and system parameters, it is easy to see how silicon architectures are being pushed to keep up with market requirements. CPU IP vendors, memory IP vendors and silicon foundries are ready with products or to support products in the GHz range of performance. However, there is one area that still lags in the race to deliver the increased performance possible from using faster silicon processes and CPU cores and memory IP. 

That area is the memory bottleneck caused by low bandwidth optimization and memory latency and requires advanced memory scheduling techniques to solve. Sonics introduced a Memory IP Subsystem product, MemMax AMP in October, 2011. This product is designed to deliver substantial increases in memory utilization and optimizes bandwidth within a system and provides Quality-of-Service (QoS) features to designers. This product provides an intelligent DRAM scheduler that can increase memory bandwidth and DRAM efficiency on-chip within a single IP block.

Memory is one of the key ingredients to any SoC architecture and efficient use of this precious resource is absolutely necessary if a SoC designer is going to get the performance out of his architecture to meet the increasing market requirements for silicon listed above. Sonics has correctly identified one of the main areas for improvement in SoCs and has delivered this solution in an IP Subsystem that is easily integrated into the SoC silicon.