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The Increasing Demand for High Speed Communications Channels
If there is one constant in our mobile, connected society today, it is the continual demand for moving more data, more efficiently and at less cost. This dynamic underscores virtually every technology and end market. It is a trend that is proving to be critical to the semiconductor industry as well as companies like Facebook and Google that participate in the efforts to create the standards necessary to deploy 400G data channels for data centers.
The high speed channel initiative is aimed at the data center. It is a certainty the high targeted speeds will allow more data to be moved more quickly into edge devices and eventually smart phones, tablets and other mobile devices. While the transition to these speeds by devices is still in the future, there is market pressure to increase the data communication capabilities of the SoCs in mobile systems.
Contemporary SoCs use multiple channels of Serializer-Deserializer (SerDes) technology; usually in the form of 3rd Party Semiconductor Intellectual Property (SIP) blocks instantiated into the silicon. The SerDes SIP is available from multiple SIP vendors in two forms: a discrete SIP block implemented as only the bare data channel (the PHY) and as a data channel paired up with one or more communications protocols like USB, PCI, SATA, etc., (The PHY and the MAC). In this second case, the SIP vendor supplies both the SerDes SIP and the communications protocol controller. The combined market for only the SerDes portion of all these SIP types is roughly $300M in 2015 and is growing at a >12.0% CAGR through 2019.
Although the SerDes SIP and the silicon design effort are both well understood, given the amount of data being moved and the speeds at which users expect their silicon to operate, the integration of the silicon solution onto the PCB and then into the target system now becomes much more complicated. In effect, this is now a systems integration effort with expertise required from fields as diverse as PCB layout, SIP design, silicon design, package design, silicon foundries, device testers and system architectural layout just to name a few.
The issues represented by successfully designing and implementing high speed SerDes channels in just one of these industry segments are challenging, let alone trying to integrate the technology across multiple disciplines and industries.
These issues will be explored during the panel "How Do We Get to Next-Generation High Speed Data Transfer Rates?" at the Semico IMPACT 2015 conference, October 13. The panel will be comprised of Lee Ritchey, Speeding Edge; Scott McMorrow, Samtec; Geoffrey Hazelett, Polar Instruments; Daniel DeAraujo, Mentor Graphics; and Nathaniel Unger, Altera. Brian Fuller, Editor in Chief at ARM, will moderate the panel.
What: Semico IMPACT 2015
When: October 13, 2015
Where: Computer History Museum, Mountain View, CA
Visit our website for more information and to register.
For more information, contact Rick Vogelei.
Phone: (480) 435 - 8564
Email: rickv@semico.com