You are here

Cadence Design Systems and the Semico IP Ecosystem Conference

Semico held its Impact conference: Focus on the IP Ecosystem at the DoubleTree Hotel in San Jose, CA on May 16th,2012.  The day before, on May 15th, Cadence Design Systems announced its first IP Subsystem product, a Storage IP Subsystem based around the new NVMe (Non Volatile Memory express) interface standard for flash-based storage applications completed in March, 2011.  This IP Subsystem provides a complete HW / SW verified solution and maximizes the command throughput for interaction between system software and the storage system.

It is intended for those applications that want to replace rotating media in a system with flash-based Solid State Drives (SSD). Vishal Kapoor, Vice President, Marketing Design IP and Services at Cadence gave a presentation at the Semico conference the very next day. He provided some fascinating insights into the forces at work behind the creation of their Storage IP Subsystem.

  • One of those forces is the increase in the cost to integrate various IP blocks into a complex SoC architecture. These costs continue to rise with each new generation of SoC largely driven by the dramatic increase in the number of IP blocks infused into the architecture.
  • Another force is the fact that application software engineers now outnumber silicon designers on most SoC design projects and the cost to create the silicon has now been eclipsed by the cost to create the software to run on the silicon.
  • A third force is the fact that silicon designers are looking to reduce the level of effort they must expend to create the advanced SoC architectures expected by end users for each new generation of silicon. The “Anytime, Anywhere” connectivity expected by mobile device users has a price and the industry is now seeing just how large that price is.
  • A fourth trend, is the simple fact that the increasing use of audio and video by consumers is pushing HDD manufactures to more than double areal densities by 2016.  HDD areal densities measuring data-storage capacities are projected to climb to a maximum 1,800 Gigabits (Gb) per square inch per platter by 2016, up from 744 Gb per square inch in 2011.

The first three forces mentioned above all point to impacts on the silicon design side of the equation and point to why design costs are rising. The last trend points to a system level performance issue not necessarily related to design cost. All of these trends speak to impacts on user experience and expectations.

This last trend is one that Semico believes is important to the emerging market for SSDs and to products like the Cadence Storage IP Subsystem. While is it commendable that HDD manufactures continue to improve the areal densities of their products, they cannot impact data transfer rates significantly because that is a system-level function and the responsibility for that part of the overall system lies elsewhere. This is one of the major reasons why the industry has suddenly developed an interest in transitioning away from rotating media and to flash-based SSDs – performance.

Another reason is power consumption.  However, just because the storage medium used in the system suddenly acquires better read/write performance characteristics or better power consumption metrics, it does not mean the system can take full advantage of them. Other changes need to be made, changes at the ‘system level’. This was the main message of Vishal’s presentation at the Semico conference; changes need to be made to the IP ecosystem so that SoC design can adopt a system-level driven approach to resolve issues like those mentioned above. The IP must be designed from a ‘system-level’ point of view from the very beginning in order to make it easier for the silicon architect to adopt and use in his design. At the same time, the IP must allow for ease of integration into the design. This is one of the main ideas behind the idea of the IP Subsystem: address and solve issues at the system level by delivering the IP as a complete product instead of as one or many discrete IP blocks the designer then must aggregate into the functionality he needs. By doing so, it should be possible to include some of the applications code necessary for that function and to have a testbench accompany that product as it migrates from one SoC generation to the next.

All these steps can potentially reduce the cost of the overall design and speed time to market. It is noteworthy that Cadence selected the storage functionality to aim their first IP Subsystem product at since this is an area that will see great growth over the next 2 – 3 years. Many system OEMs want to use SSDs in their products to reduce weight and power consumption and increase performance. Products in the form of an evolved, integrated, contiguous IP Subsystem will generate a great deal of interest from prospective customers.