Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect
 
by Richard Wawrzyniak: Principal Analyst; ASIC and SoC
Semico Research Corp.
 
Dynamic Power Management has become a 'must-have' in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.
 
Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel.
 
The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today.
 
Market Requirements Drive Power and Energy Targets
 
Today, there is a constant evolution in market requirements for silicon solutions targeted at mobile applications. This is primarily driven by user demands for more functionality while delivering greater ease-of-use to the end user. All these advanced features and increased functionality come at a price; greater power consumption and rising device complexity.
 
Competition in the mobile markets is also very intense and silicon must not only be cost effective, but must be competitive with other solutions in the marketplace. Requires a collaborative effort between the different SoC design teams: Verification, Silicon and Software and with Marketing, is necessary to identify, set and meet the goals needed to make the design competitive.
 
To meet these moving targets, SoC designers and silicon architects must craft their solutions with an eye towards constrained thermal footprints and expanding power delivery and control mechanisms. In many cases, all the device’s transistors cannot be turned on simultaneously without severe consequences to battery life and heat generation. Mobile applications depend on maximizing battery life and methods to conserve power have become a priority in most SoC designs. This puts an emphasis on the SoC design team to make the best possible choices and tradeoffs between device functionality, operation and performance. It is not surprising to learn that architecting proper device operation at minimized power consumption levels has assumed a pre-eminent position in the design hierarchy. In some of the more complex designs, 70% of the design effort is taken up by emplacing the correct power management control structures and then performing the verification effort on the silicon and the software, ensuring power consumption is kept to a bare minimum without sacrificing performance.
 
Highest Design Leverage Comes at the Architectural Level
 
In order to ensure that power consumption is kept to acceptable levels, it was necessary to enact an architecture-first approach. This allowed the design team to focus on setting power consumption goals and choosing power management technique for the different functions needed in the silicon early in the design instead of waiting for the RTL, logic gate or physical implementation level. Addressing these issues at the RTL/gate level would come too late in the design process for the design team to meet its stated goals for power reduction versus previous designs and preclude the chance to achieve the desired power management of existing and new features.
 
The power management architect today needs to understand many different aspects of the SoC design in order to embed the correct mix of control features into the silicon. Applying today’s techniques requires a deep understanding of clock gating, power gating, save/restore features, DVFS and more. Good communications skills for the power architect are necessary to interact with all the design groups, to accurately and efficiently state needed power management and energy management goals, and to communicate the impacts of different design tradeoffs to all the groups involved in the effort.
 
In many cases the automated tools necessary to aid in this communication effort are not very powerful or are lacking altogether. Many times, the modeling necessary to develop and communicate the different design goals and tradeoffs is done with Microsoft Excel and Word files shuffled between the different design groups. Integrated tools that allow sophisticated modeling of power states and with multiple iterations over time are not available from the market at large. Work-arounds are the order of the day for the power management architect today.
 
High Design Complexity – and Getting Worse
 
Semico tracks the 3^rd Party Semiconductor Intellectual Property (SIP) market along with the SoC market and the ASIC Design Start market. Our research points to increasing numbers of SIP blocks being used in SoC designs today and especially at the advanced nodes. It would not be uncommon to see a complex SoC today with upwards of 200 SIP blocks being integrated into a contemporary part.
 
This can cause several issues within the design flow:

1. Increasing number of SIP suppliers being used
2. No common method to create the blocks
3. No common method to formulate the deliverables given to the user
4. The way power states are handled by the individual blocks can be different
5. Effort to integrate all the different blocks is increasing due to rise in individual block complexity and rise in the number of blocks being used
6. Interfaces between the blocks are not standardized

 
All these issues add to the size and complexity of the integration effort that must be expended by the design team to ensure all the blocks can efficiently interact in the design. To ensure all the aspects of the individual SIP blocks interact correctly, and still meet design timeline goals, the size of the design teams has increased over time.
 
Jawad commented on how growing device complexity has influenced the growth in design team size over time: "If I’m looking at the power management architecture team today, it’s about 4X the complexity today than it was before in 2010. The requirement for power management has grown, for example, for mobile computers and laptops, it has nearly the same requirement as phones. You need 8 hours (of battery life)."
 
Jawad went on to say:
The design complexity is growing and also the team is growing. Companies are hiring more power management architects for the power team. Also the various blocks or IPs have someone working with the central power management team, in order to keep the central power management team as one entity."
 
Jawad also gave me some of the particulars on the size of design teams and the complexity levels they are dealing with.
 
"Power management is very difficult. A lot of design teams are in the dark. For a large SoCs, you can need a team of 10-15 power management architects. In addition, you will see the same amount of people on the design side. The verification team has between 20-30 people working on the verification side. It is very complex because of the interaction between the various components of the CPU. Also there is a local power management for each functionally unique block. There is a local power management and global power management which has messages from the local units until one central decision like going into an idle state or changing the frequency and the voltage. The components like the cores or the memory…it’s a very complex task for these SoCs with many components integrated inside the SoC."
 
While a company like Intel has the available engineering resources to dedicate to multiple designs of this complexity, one has to wonder how smaller companies, attempting designs of similar complexity, can do so with much more limited resources available to focus on the design. Design tools and/or SIP of sufficient capability are a way to increase designer efficiency, but so far not many tools exist that deliver the right level of flexibility, modeling, programmability and control that smaller companies can use in their design efforts.
 
Opinion on the Sonics EPU
 
Jawad had an opinion on the EPU concept and some suggestions for future iterations and improvements:
 
"I was in the seminar where they presented the EPU. I think it’s very interesting methodology and concept. I think this is the first time that I see a company that tries to tackle the power management problem as a whole. The EPU is going to do communication. How to communicate (between) one component, one IP and the central controller. I think this has a way to go. Next revision should include thermal capabilities and more looking at the global power management. Concepts like thermal, battery life, and performance. Other options for post-silicon capability for the architect to customize in post-silicon in the design."
 
Based on the design teams' activities, an SIP-based approach to creating an on-chip infrastructure that deals with power management related issues is very interesting from an architectural design viewpoint. This allows the power management architect to embrace a management and control structure that has a very fine granularity that can connect all the power management methods being used in the design to one central location. In addition, the ability to rapidly model multiple SIP blocks and their power states simultaneously allows for a much better, real time information flow to the power architects and empowers them to make multiple 'what-if' changes before finalizing their design.
 
Having such an embeddable infrastructure with communications links back to the architects enables a much finer level of control over the various power management methodologies being used. In addition, since by definition the Sonics infrastructure allows connection of all these disparate SIP blocks in the design to each other, the flow of information between the blocks is greatly enhanced and the level of effort necessary to connect all these blocks is greatly reduced, freeing up valuable time to the architects.
 
The introduction by Sonics of an embeddable infrastructure that allows for advanced modeling scenarios and control of individual SIP blocks down to the state machine level provides great flexibility to the users and extends their control over the feature sets and functionality designed into the silicon. Jawad hoped that Sonics can make further additions to the functionality in their EPU product in the future including defining enhanced standards for interfacing different SIP cores together. The Sonics EPU product goes a long way to solving many of the issues faced by power management architects today when designing complex SoC solutions.
 
As we have previously seen in the semiconductor market, the evolution of functionality and feature sets in complex SoC silicon is a moving target that quickly responds to changing market requirements. With this product introduction, Sonics has put in place a vehicle to define future functions and create a roadmap that power management architects can follow and innovate with. A very welcome development in the SoC market indeed!