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Boards, Chips and Packaging:
Designing to Maximize Results



7:30am - 8:30am Registration and Continental Breakfast
8:30am - 8:45am Welcome & Outlook - Jim Feldhan, Semico Research Corp.
8:45am - 9:15am Michael Gay, Isola  --  Abstract
9:15am - 9:45am Daniel DeAraujo, Mentor Graphics  --  Abstract
9:45am - 10:15am Break
10:15am - 11:30am Panel:  How Do We Get to Next-Generation High Speed Data Transfer Rates?
Moderator:  Brian Fuller,
Lee Ritchey, Speeding Edge
Scott McMorrow, Samtec
Geoffrey Hazelett, Polar Instruments
Daniel DeAraujo, Mentor Graphics
Nathaniel Unger, Altera
11:45am - 12:30pm Lunch - Sponsored by Isola
12:30pm - 1:30pm Keynote:  Chesley B. "Sully" Sullenberger, III
  Afternoon Session:  Innovation Spotlight
1:30pm - 1:50pm Robert L. Sankman, Intel  --  Abstract
1:50pm - 2:10pm Margaret Schmitt, Ansys  --  Abstract
2:10pm - 2:30pm Break
2:30pm - 3:45pm Panel:  Boards, Chips & Packaging:  Meeting Market Requirements
Moderator:  Mike Noonen,
 Ambiq Micro
Jason Marsh, Insulectro
Heidi Barnes, Keysight Technologies
Nathapong Suthiwongsunthorn, Ph.D., UTAC
Tom Whipple, Cadence
3:45pm - 4:00pm Closing Remarks


Critical Industry Issues

(Event will include 2-3 panels)

Panel 1- How Do We Get to Next-Generation High Speed Data Transfer Rates?

The need for more bandwidth is continuing to drive the Internet infrastructure. Rapid growth of server, network and internet traffic is fueling the need for higher data rates. Key contributors to data demand include Internet consumer applications, cloud-based computing and storage, virtual servers, advances in scientific and financial computing and the Internet of Things. While fiber optic cables are capable of delivering data rates into terabits/sec, the main bottleneck continues to be the last critical mile solution. Deployment of FTTH (Fiber To The Home) and the emerging 60 GHz point-to-point microwave links, which enable Gb/s rates to the home, are seen as viable last mile solutions.

As a result:

  • On-board transmission rates are moving to 100 4X25-32 Gb/s per channel. IEEE standard 802.3bj standard is defining 4-lane PHY for operation over PCB backplanes.
  • The main enablers for higher data rates will include 64B/66B coding on high speed SERDES devices with ~97% efficiency; advances in phased locked loop technology; improved dielectrics with almost zero loss; improved profile free copper to reduce conductor loss; equalization and emphasis technologies such as decision feedback equalization, feed forward and adaptive equalization techniques powered by FPGAs and better connector technology.
  • Differential signaling is the preferred choice for high speed SERDES devices so as to avoid the use of higher frequency harmonics.
  • At higher frequencies (beyond 10 GHz) skew, caused by the fiber weave effect, is the biggest barrier to reaching high data rates.
  • The ability to go beyond 56 Gb/s will include the use of effective multilevel signaling techniques such as PAM 4 and mitigating and eliminating the skew generated by the fiber weave effect.

The panel will be comprised of a Lee Ritchey, Speeding Edge; Scott McMorrow, Samtec; Geoffrey Hazelett, Polar Instruments; Daniel DeAraujo, Mentor Graphics; and a representative from Altera. Brian Fuller, ARM, will moderate this panel.

Panel 2- Boards, Chips & Packaging:  Meeting Market Requirements 

The Internet of Things promises an unprecedented opportunity for the electronics industry.  From front-end devices like roadway sensors to back-end network equipment supporting the rush of new data inputs, electronics are the integral foundation of this new era.  More than ever, pressure is on the electronics industry to deliver the right solution at the right time and at the right price. 

Product design is the foundation for each successive stage of the product development process and every player in the electronics ecosystem feels the pressure from the interdependence each time a product hand off occurs.   Delivering market tested electronics with precise designs demands coordination at all levels of product development.  All players are recognizing the need to collaborate throughout the design process including chip design, package design, material selection and board design to solve problems they all face together.

Designers across the electronics ecosystem must come to the table to address issues such as:

  • Parasitic capacitance and inductance issues that impact signal integrity;
  • Board material characteristics to deal with varying frequencies, especially high frequency;
  • New package form factors such as thinner packages and 2.5D and 3D packages;
  • Packages with tight interconnect spacing creating board design issues;
  • Board layout techniques to avoid cross talk, EMI, and short circuits;
  • Shorter design cycles with added cost pressure; and
  • Designing boards for maximum power reduction and heat dissipation.

Products are more complex than ever before, with unique design requirements ranging from high performance to low power.  Well-defined product development specifications are critical to getting a product that performs right the first time.  Collaboration involving each step of the process—from chip design, package design, material selection to board design—will help us all achieve our shared goal of delivering first-time-right products. 

This panel will wrap up the event with insights and solutions that will help you implement successful product launches and grow your markets.  

Other Possible Event Discussion Topics

Autonomous Driving: Who’s Behind the Wheel?
The advanced driver assist systems applications used in current and future generation automobiles cover a broad spectrum of performance and feature enhancements.  Elements currently in use today include a fusion of technologies such as:  adaptive cruise control, collision avoidance, blind spot detection, lane departure warning, stop-and-go systems, side impact warning, cross traffic alert, evasion maneuver, pedestrian protection, front collision warning, proximity warning and parking assist functions. These systems use a variety of technologies at varying frequencies to achieve the specific system performance.
Currently systems operate in the 24 GHz and 77-81 GHz frequency spectrum and could very well exceed 100 GHz in the future as the technology evolves.
Autonomous driving is viewed as the next stop on the road to automotive innovation.  The ultimate goal for these unique technologies is first and foremost safety, with the ultimate goal of assisting in achieving an autonomous driving experience.

  • What are the key technologies enabling autonomous driving?
  • Which wireless standards will dominate vehicle-to-vehicle and vehicle-to-infrastructure communications? 
  • Which technologies will enable sensing that supports safety for autonomous driving?
  • Which semiconductor technologies offer performance and cost features to meet the needs of autonomous driving?

Currently five technologies are considered to be essential enablers for autonomous driving, which include lidar, radar, sonar, optical and vehicle-to-vehicle communication systems. With the advantages associated with 77 - 81 GHz technology, these requirements may distill down to three essential technology platforms namely Radar, Optical and Vehicle-to-Vehicle communications.

  • What are the cost issues? 
  • What technologies will help to reduce cost? 

These questions and more will be addressed by panel participants from an IC manufacturer, a major auto manufacturer, a material supplier and a Tier I auto supplier. 

RF/Digital Hybrid boards

Advanced chip manufacturing technology and new design techniques have enabled the integration of RF chips with digital circuitry creating a RF/MW circuitry solution. Building boards using different dielectrics and routing digital wave forms and RF signals through specific layers enable a reduced footprint. Chip manufacturers are working to pack more and more functionality into the ICs resulting in a reduced number of features on the dielectric. All the attempts at integration are resulting in higher power density leading to requirements for higher power dissipation, lower thermal resistance and the need for stability of dielectric properties in regard to temperature and frequency. Further, the use of turbo coding and signal processing techniques has made the communication bandwidth approach the theoretical Shannon limit. This has led to focusing on increasing the bandwidth through smaller cells. These networks will be comprised of macro base stations coupled with smaller micro, Femto and Pico cells that form the heterogeneous networks, or Hetnet. Heterogeneous networks rely on very small cells which can cater to a group, office, building or a set of buildings. The communication is mainly digital and could be fed through point-to-point links or wireless links. The circuitry required is hybrid to a certain extent with RF or digital on the receiving or transmitting end. The reliability needs for such hybrid boards are driven by extremely tight pitches on the components leading to concerns relative to CAF, delamination, drilling, plating and other processes. These reliability requirements, coupled with the HDI designs and requirements for high heat dissipation, are making RF/high speed digital board manufacturing increasingly complex.

This panel will be comprised of RFIC manufacturers, wireless infrastructure manufacturers and board manufacturers that will address the challenges posed by these new hybrid, single-board requirements.

Phased Array Antenna Solutions

Conventional satellite communications require that a narrow radio frequency (RF) beam be directed on a receiver (usually a parabolic dish). If either the sender or the receiver is moved, the direction of the narrow beam must be kept by pointing the beam to the accurate position on the satellite. This positioning is achieved through the use of a motorized mechanical gimbal that moves the parabolic dish such that the beam remains focused on the satellite. In contrast, phased array antennas provide an enhanced level of performance by pointing or steering the beam from an array of fixed antennas eliminating the mechanical hardware and increasing the speed of movement. Increased performance characteristics of phased array antennas include:

  • The ability to steer the beam faster
  • Better level of steering through electronic means as opposed to mechanical means
    • Resulting beam can be controlled and directed immediately in any direction
  • Increased communication performance

This panel will discuss the hardware required for phased array antennas, the challenges in building them and the future potential of the antennas.

For more information contact:
Jim Feldhan
602-997-0337 Opt #1

Joanne Itow
602 997-0337 Opt #2

Kella Knack