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IP Subsystems: The Next IP Market Paradigm
The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures the entire electronics market has undergone, it is the 3rd Party SIP market.
Most of these evolutionary forces are driven by the need to integrate more functionality in fewer devices at the system level and in ever-smaller footprints. One method to accomplish this is through the use of 3rd Party SIP. However as design costs and time to market pressures mount on SoC designers, it is becoming more and more difficult for these designers to craft their silicon solutions in a timely and cost effective manner.
Enter the IP Subsystem, organized by system-level functionality and around its own internal interconnects, as one contiguous block accompanied by its own testbench of verification IP and small to large amount of applications software.
The IP Subsystem is the method SoC designers will employ to infuse the right level of complexity and functionality into their silicon solutions to meet quickly changing market requirements without experiencing a corresponding increase in design costs or design cycle time. Larger parts of the design can be dealt with at one time opening the door for the applications software to be written in parallel for each subsystem used in the design.
Large IDMs and OEMs have been creating such subsystems out of the IP blocks they have either licensed from the 3rd Party or created themselves internally for the last several years. These companies have used this concept as a method to competitively differentiate themselves from their competition and to make the SoC design process more manageable. Now, for the first time, 3rd Party SIP vendors are about to enter the market with commercially viable products that can replace the internally generated efforts of the large IDMs and OEMs.
Some companies understand the implications and are already taking advantage of these new options. Others are still trying to figure out what it means. Which one are you?
I have just completed a new report for Semico Research, IP Subsystems: The Next IP Market Paradigm; SC106-10, in which I detail all the forces and trends mentioned above along with forecasts for the seven IP Subsystem types we see comprising this market today.
Rich Wawrzyniak
Senior Analyst
Comments
We decided about over a year ago that IP, as well as SoCs were of major interest to Zocalo for two reasons.....one of our primary consultants is an IP provider and educated us on the assertions and IP....and an article on IP that had some interesting statistics and a quote that really hit home:
“Third-party semiconductor IP is now a $1 billion per year business, with thousands of suppliers. One-third of all logic in a design is now reused legacy IP, and that figure will grow to 50 percent by 2015” (ITRC – International Technology Roadmap for Semiconductors).
“...making 30 percent of your design from reused IP blocks doesn’t mean you’re going to be 30 percent more productive at the end of the project. That’s because IC design teams tend to underestimate the work needed to implement the IP.” per Ron Collette, CEO Numetrics.
The value proposition of IP is the reuse of commonly used design components integrated within SoCs. However, the time and cost of integrating IP with the custom logic negates or minimizes the value of reuse.
It is generally accepted that adding complex high quality assertion as part of the IP deliverables can have a major impact on this issue. However, the number of people that can create and debug this level of assertions makes it easier said then done and rarely happens.
Our product Zazz is directed to enabling effective Assertion-Based Verification. Although SoCs are our primary target market, we include IP as a secondary target market because of its strategic importance to SoCs
Hi Howard,
Thank you for your comments - I appreciate them and your interest in the IP Subsystem concept!
I would say you are correct about the difficulty in adding high-level assertions to an already complex SoC design. It is not something that is easily done.
This is why I was so interested when I first heard about the IP Subsystem concept - it changes the focus from designing with many individual IP blocks to designing with system-level functionality. I believe it can be a game changer for many SoC designers if applied the right way.
I think your approach to enabling SoC design through Assertion-Based Verification is going to become much more important to SoC designers and IP Subsystem vendors alike in the near future. I beleive most-if not all, IP Subsystems will have a testbench accompanying them as a deliverable and this will include the verification IP as well.
I think you are in the right area of the market to see new customers and growth opportunities going forward.
Please let me know if you have any questions or if you would like to discuss these concepts further.
Best regards,
Rich Wawrzyniak
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