You are here

November 2013

What I Learned on the Way to the Semico Impact Conference: Focus on the IP Ecosystem

I had a very interesting discussion with Sundar Iyer, CEO of Memoir Systems, during a briefing they gave Semico on their just-released Pattern Aware Memory IP technology.

To briefly restate their announcement: Memoir has researched the different interactions between processors and memory in high-performance datacom systems and found that certain operations recur fairly often.  These operations roughly fall into four groupings: Counter Memory, Sequential Memory, Allocation Memory and Update Memory.  There are probably many more than these types, but Memoir is starting with these operations to begin with.

Memoir Systems is a 3rd party memory IP company and, as such, devotes its time to developing and introducing embedded memory IP to the market. In the case of this new product announcement, the memory IP they are introducing is tailored around the four functions mentioned above. In other words, their memory IP is now configured to better support these specific operations at the memory level and not through software at the processor level in the system. This has large implications for system performance and throughput.

IP Ecosystem Solutions for Complex Systems

At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fellow; and Warren Savage, President and CEO, IPextreme.

Tirupattur skillfully pulled both humorous and discriminating observations from the foundry perspective, the EDA perspective and both a large and small IP vendor.
The topic of the panel was the high cost and risk of integrating IP in today’s semiconductor product development. There’s a massive risk of product failure from choosing the wrong IP, the wrong supplier, the wrong fab, or the wrong process. A misstep means jobs could be on the line. Today, complex SoCs are not comprised of just one or two IP blocks, it’s a battalion of IP coming from a variety of sources. Dan Kochpatcharin of TSMC noted that at the 20nm node an average design has 12 unique IP blocks. That compares to an average of only eight at the 28nm node.