The gap between time-to-market and design completion continues to lengthen as chip complexity increases.
Unfortunately, just as design cycle times have lengthened, product life cycles have shortened, a difficult dichotomy to manage. Increasing capability in terms of gate counts and the impact this has on enhancing functionality and feature sets in the end system, is adding to, not shortening, design cycle times. SoC designs are comprised of complex silicon subsystems, aimed at a system-level solution.
One or many high-performance synthesizable CPU cores, DSP cores, GPU cores, a large block of memory, one or more ‘real-world’ interfaces, mixed-signal or analog blocks, high performance on-chip bus structures and embedded API’s or other software are all elements of SoC design today.
The ability to re-use existing Semiconductor Intellectual Property (SIP) blocks over the course of many SoC designs is one way to reduce the design time. Unfortunately, there are many issues to be addressed. One such issue is interoperability between SIP. Another feature of the SoC market is the willingness of established silicon manufacturers to solicit and acquire SIP from 3rd party sources for incorporation into a currently running design or into their SIP libraries.
