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Constellations Track

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The Constellations Technical Track will feature concise, “deep-tech” presentations targeted at conference attendees wishing to examine IP-related topics not often seen outside the pages of a white paper. While marketing and business development executives enjoy the quality industry trend analysis and discussion that have come to be synonymous with Semico Research Corp., engineers and design teams can break out for an afternoon session that caters specifically to them. In thirty-minute sessions, presenters will delve into today’s cutting-edge IP technology and related methodologies to equip attendees with knowledge they can put into practice within their own companies.






Top 10 Reasons Why Internal IP Reuse Fails and What You Can Do About It

Warren Savage, President & CEO

Recore Systems

Reliable Data Processing In Outer Space

Gerard Rauwerda, Founder & CTO

Ridgetop Group

Using IP to Characterize the Reliability of Your Foundry’s Fabrication Process

Andrew Levy, Vice President of Business Development

Certus Semiconductor

Do You Know What ESD Really Is?

Stephen Fairbanks, Co-Director


An Algorithmic, Objective Quality Metric for Synthesizable IP

Michael Johnson, Manager of Customer Solutions Delivery


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Top 10 Reasons Why Internal IP Reuse Fails and What You Can Do About It


For almost 20 years, the semiconductor industry has been touting the importance of IP reuse. But in fact, semiconductor companies have themselves struggled with how to effectively design and reuse their own IP.  They are often far better consumers of 3rd-party IP than developers of their own IP. In this face-paced presentation we will share the top ten reasons why most semiconductor companies do a poor job of reusing their own IP and what steps your engineering organization can take to achieve greater success.


Warren Savage is a well-known and perhaps one of the most recognizable figures in the semiconductor industry. He has spent his entire career in Silicon Valley working with leading companies including Fairchild Semiconductor, Tandem Computers, and Synopsys where he focused on the problem of building a global scalable semiconductor IP business. In 2004, he founded, and still leads IPextreme in the mission of unlocking and monetizing captive intellectual property held within semiconductor companies and making it available to customers all over the world. He holds a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine University.

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Reliable data processing in outer space


The amount of data produced during space missions has increased significantly in the recent past, while the communication bandwidth from a space vessel to earth has stayed more or less the same. Industry and space agencies are urgently looking for new data processing platforms that extract and compress relevant data on board of a space vessel, to replace the current European rad-hard DSP processor which lacks performance for many applications. In space, occasional extreme radiation levels cause errors in (digital) data or during data processing and special effort goes into making data processing systems resistant to radiation.

Combining radiation hardened hardware with fault-tolerant software is the most promising option for radiation-resistant data processing solutions for space. In his talk, Gerard Rauwerda explains techniques for fault-tolerance in many-core systems, which Recore has developed together with European academic institutions in various research projects. He shows how Recore married new concepts for self-repairing reconfigurable chips to proven space concepts (LEON, SpaceWire) in a functional FPGA prototype for space applications for ESA, the European Space Agency. And last but not least, he will look to the future of radiation-resistant many-core data processing platforms and their programmer friendliness.


Gerard Rauwerda is founder and CTO at Recore Systems. His interests lie in fault-tolerant many-core data processing platforms and programmer-friendly efficient parallel programming of many-core systems.


Using IP to Characterize the Reliability of Your Foundry’s Fabrication Process


Fabless semiconductor vendors typically rely on their foundries for data that describes the reliability of the underlying fabrication processes the vendors use to implement their ICs. Some of the larger fabless companies develop their own data but it is a very costly and lengthy process. This presentation discusses a new, foundry-independent methodology for examining process reliability issues affecting today’s deep submicron processes. The supporting tools and services are low-cost, have much higher throughput than existing methods, and can be targeted specifically at the devices and failure mechanisms of most concern to the fabless companies. The presentation will also briefly cover die-level process monitors (DLPMs) for yield enhancement, in situ reliability monitors to warn of IC degradation effects, and a library of high reliability analog/mixed-signal IP for data converters and their building blocks.


Andrew Levy is Ridgetop’s Vice President of Business Development. Mr. Levy is responsible for Ridgetop’s growing business providing advanced semiconductor test structures, IP cores, radiation-hardened ADCs and precision reliability characterization instruments. Mr. Levy brings a significant amount of IC industry experience. In particular, he has expertise and published papers regarding IC test applications, design-for-test of ICs and PCBs, and software for developing ICs and IC test programs. He was a co-founder of Teseda, a ground-breaking desktop test instrument firm, has served in various managerial roles in the semiconductor field, including Credence, Opmaxx, and IMS. In addition to his broad managerial and business background, Mr. Levy has made many technical contributions to the semiconductor industry. He holds a patent for design-for-test (DFT) IC test technology, led an award-winning semiconductor test application engineering group at IMS, published many technical papers and articles, and served as technical expert for digital, analog, and mixed-signal IC test methodologies and tools at several companies. He began his career at Intel Corporation where he led a microprocessor application group, was a program manager for a state-of-the-art microprocessor, and held a number of key software engineering and engineering management positions. He received his BS in Mathematics and Computer Science from UCLA, and an MS in Computer Science from the University of California, Berkeley.

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Do you know what ESD really is?


This Presentation will introduce engineers and managers to the latest concepts, understandings and research regarding Electrostatic Discharge (ESD) and Electrical Overstress (EOS) as they relate to current trends in reliability, manufacturing yields and field returns.  Everyone knows what ESD is, but few really understand how ESD qualification levels and standards affect or relate to yields.  Even less is understood regarding EOS and IEC, and what they are.  Knowing the differences between these three types of threats can mean saving months of debug work and lead to faster solutions for yield issues in the manufacturing environment.  This tutorial seeks to create a clearer understanding of these critical topics for all individuals involved in semiconductor design and manufacturing industry.


Stephen Fairbanks was the lead ESD design engineer for Intel’s Wireless and Communications groups from 2002-2006.  In 2006 he left Intel to found SRF Technologies, which continues today as one of the world’s leading ESD and IO design service companies.  In 2009 he partnered with Markus Mergens of QPX to create Certus Semiconductor, a company specializing in the IP licensing of IO and ESD libraries.  He has been dealing with ESD, EMI, EOS in analog, digital and RF IO designs for 15 years.

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An Algorithmic, Objective Quality Metric for Synthesizable IP


The use of heterogeneous IP is on the rise for all SoC designs.  More of this IP is now soft, or synthesizable as well. Since soft IP has many possible implementation configurations, the task of validating the quality and completeness of this form of design data is daunting.  Deficiencies in areas such as routability, testability or power consumption can cause substantial tape out delays.  In their worst form, these problems can cause the entire SoC project to fail. In this presentation, we will explore a comprehensive IP quality auditing system developed by Atrenta to address this issue.  Using the Atrenta IP Kit, IP consumers can substantially reduce IP reuse problems and have a much better view of the integration risks for any soft IP block.


Michael Johnson is manager of Customer Solutions Delivery. He has over 20 years of experience in IC design, EDA tool development and field applications.  He has worked with customers worldwide to help them develop effective methodologies to address highly complex design challenges. Prior to Atrenta, Michael worked at Raychem, Philips Semiconductors, TransEDA and Cadence Design Systems. He holds a Bachelor's degree in Electrical and Electronics Engineering from the California Polytechnic State University-San Luis Obispo.