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May 2013

Ring of Fire Poses Risk to Semiconductor Manufacturing

Adrienne Downey's picture
published by Adrienne Downey on Thu, 2013-05-09 00:23

There are hundreds of semiconductor fabs, spread all over the world. The trend over the past several years has been one of consolidation into several main manufacturing centers in the Asia/Pacific region, the United States, and Europe. Unfortunately for the industry, many of these fabs are located in areas prone to earthquakes. Some locations are also at an added risk of damage from tsunamis generated by earthquakes.

The northeast coast of Japan is a prime example; in March 2011, the region suffered a massive 9.0 magnitude earthquake and tsunami that killed 15,883 people, injured over 6,000, and left almost 2,700 still missing. The disaster also caused seven meltdowns at the Fukushima Daiichi nuclear power plant. The plant is still running on makeshift equipment and recently suffered a power outage that left four fuel storage pools without cooling water. In terms of damage to buildings, almost 130,000 buildings were completely leveled, and over a million others sustained some sort of damage. The amount of devastation was astounding, but the Japanese have done an amazing job of clearing away debris and recovering in the two years since, as illustrated by these photos posted at the Atlantic.

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IMPACT Conference

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Semico IMPACT Conference: Focus on the IP Ecosystem

Doubletree Hotel, San Jose, CA November 6, 2013

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Semiconductor IP continues to be a crucial component in the design and development of complex integrated circuits, especially SoCs. This Semico IMPACT Conference will focus on the IP ecosystem and issues that are affecting the growth of the semiconductor industry.

From Basic SoCs to Advanced Performance Multicore SoCs, designs are evolving into new forms, enabling a variety of enhancements to existing end applications.

  • As device structures change and complexity increases, how are companies managing time-to-market versus chip complexity versus cost? Does it pay to wait?
  • How do derivative designs drive new designs? Are new architectures postponed because of the availability of derivatives?

IP subsystems, the holy grail or marketing hype?

  • What do third-party IP suppliers bring to the table that would encourage IDMs to pursue a "buy" versus "make" decision? Is a third-party IP subsystem a necessary evil or a productive way to solve design issues?
  • Which IP subsystems are getting the most traction?

Changes in the IP market are prompting enhanced and more comprehensive tool sets from the EDA vendors. What can we expect in the future regarding more highly integrated and intelligent EDA tools to aid in infusing more complex IP blocks into SoC designs?

As designs become more complex, so too has the size of the verification effort. What is the current understanding of EDA vendors of this issue and what can be done about it? Where will it be in the near future? What do EDA and IP vendors see as the future of verification IP in relation to the total design effort? Will verification IP ever be used in the design of the SoC silicon itself?  

The Semico IMPACT Conference “Focus on the IP Ecosystem” will provide a lineup of thought-provoking keynotes and enlightening panels. If you are a silicon architect, an SoC designer or an ASIC design manager, plan to attend this event on Wednesday, November 6, 2013 at the Doubletree Hotel in San Jose, California.

 

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Our analysts update the Model throughout the year, providing historical data from 2000 and forecasts out 5 years. Our MAP Model takes both the top-down and bottom-up approaches and combines them into one customizable service for analyzing Wafer Demand, Semiconductor Content, Bill of Materials, Total Available Market, End-Use Shipments, and ASPs in over 30 different markets including:

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Photos: (left) Dean Kamen and Jim Feldhan. (right)Dr. Tsugio Makimoto, Dr. John Kelly III, Jim Feldhan and Wally Rhines.

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