TSMC Expanding the Ecosystem

Last week TSMC held their annual Technology Forum in San Jose.  Even though Rick Tsai and the management team presented a cautiously optimistic outlook for this year, they are investing heavily for the future.  Sounding much like Intel, TSMC is increasing their investment during the downturn, investing in innovation to prepare for the upturn.  R&D expenditures in 2009 were originally expected to be flat compared to 2008.  TSMC announced an increase in R&D.  Expenditures will be up 20% and will target the following areas.

1. Increasing R&D process engineers by 30%, reaching a total headcount of 1200

2. Increasing Design Technology engineering staff by 15% to 600 total

3. Accelerating investment in leading edge 22nm technology

4. Expanding research efforts in mainstream technologies or “more than Moore”.  That includes sensors, power ICs, LCD drivers, data converters, MEMS, LED drivers, RFID

5. Supporting a worldwide research effort with a new facility in Leuven, Belgium

6. The creation of a System in Package research team that will focus on Through Silicon Via (TSV) or 3-D packaging 

7. Added efforts in the design/IP preparation and setup

8. Continuous capacity investment

TSMC’s support of the EDA/IP setup is no surprise.  They estimate that by integrating EDA qualification and IP validation at the same time as process development, customers can reduce design cycle time and time to market by 3 to 12 months.  They also manage to “lock-in” customers with proprietary tools.

To put dispel any fears of capacity shortages in the next upturn, TSMC proudly presented Fab 12, Phase 4.  With a cleanroom the size of eight football fields, the new facility will house both volume production activities and be the TSMC R&D headquarters.   Production equipment move-in is set for June 2009.  Production is expected before the end of 2009.  In addition, R&D equipment for 22nm will be installed before the end of the year.  There will also be a new 300mm TSV pilot line installed in 2009.  

TSMC is expanding their role in chip design, in tool support, and in new packaging options in the back end .  The two surprising aspects of this tech forum were the research being conducted on multiple e-beam lithography and the absence of much information on 28nm technology.  I was surprised to hear that TSMC is betting on both EUV and e-beam for next generation lithography.  EUV is more appropriate for high volume runners while multiple e-beam could be the solution for low volume ASIC customers.  Very insightful.  Why wasn’t there any mention of 28nm in the keynote presentations?  I believe it was because TSMC is not going to push the technology transition yet.  There is certainly a lot of life left in 65nm, 45nm and 40nm processes.   

Joanne Itow

Managing Director