SST All-in-One Memory

On Monday, SST announced an innovative new way to approach the memory requirements for a wide range of products. The All-in-OneMemory is a multi-chip package (MCP) consisting of three chips: NAND, RAM (DRAM or PSRAM), and a controller. The advantage this brings is the processor only needs a single RAM bus to interface with code storage, data storage, and RAM all at the same time. The type of RAM used depends on the density needed; under 512Mbit, they’ll use PSRAM. DRAM will be used for systems needing 512Mbit and more.

The NAND simulates NOR by using the RAM as a cache; SST calls this Pseudo-NOR, which is very appropriate because it is similar in concept to Pseudo RAM. This enables SST to offer execute-in-place (XIP), even though the system is based on NAND. The controller chip includes embedded NOR flash. The RAM is partitioned; part of it is used as cache, and part is used as system memory. Perhaps the most interesting aspect of the solution is the ability to partition part of the NAND as a memory-mapped ATA disk drive. The partitions are configurable so that system designers can customize the MCP to suit their needs.

All-in-OneMemory is targeted at applications that require high levels of code and/or data storage. These include the wireless, consumer, networking, and computing markets. It enables fast time-to-market due to its simple interface, but provides high reliability with the testing they provide. The reduced complexity of the system design also reduces total system costs. SST has not announced pricing yet; their solution could command a premium over the total sum of the individual parts because it reduces board space, time-to-market, and design time.

The solution will be introduced in the second half of this year.