Is the SoC Design Environment About to Change?

On 7/27/09 at the Design Automation Conference (DAC) in San Francisco, ARM, Chartered Semiconductor Manufacturing, IBM, Samsung Electronics and Synopsys announced an agreement to establish a comprehensive technology enablement solution for SoC designs targeted at the mobile internet space specifically for the 32nm and 28nm process geometries.

While collaborations and partnerships between different semiconductor companies and other members of the ASIC design ecosystem are nothing new in the industry, this announcement has the look of something different for the ASIC market.

Essentially the participants have aligned their technology roadmaps, technology development, products and design tools to enable an all-encompassing environment for complex SoC designs. In fact, Synopsys showed a diagram of a single design suite that allows a designer the possibility to craft a complex SoC using a fully integrated suit of tools. It also allows for the incorporation and use of different IP blocks, supplied by both ARM and Synopsys, that are already pre-verified and characterized. This is definitely a step forward for the industry.

One of the very important aspects of this collaboration is the availability of a process technology that employs high-k metal-gate technology to reduce gate leakage while at the same time providing increased scalability and reducing overall complexity.

Some questions remain however.

One of the troublesome areas in SoC design, especially at the advanced nodes, is the availability of the right mix of IP blocks to use in the design. At the top of the list of IP blocks necessary for any design is access to the right embedded memory technology. While both ARM and Synopsys, and for that matter IBM, have embedded memory technologies, are they the right ones for designs of this complexity? Another question to be answered is what if the customer wants to use an IP block from some other IP company? Is there a way to add additional IP providers to the mix of partners?

Semico suspects that the long term answer to these questions is yes. It is still early days yet for all the pieces to be in place in an undertaking of this magnitude. The partners have been collaborating for over a year on this project and it is understandable that not every aspect of the collaboration is completed yet.

It would seem that the IBM Common Platform initiative is very serious about providing the very best ecosystem and environment to potential designers of silicon solutions for the 32nm and 28nm process nodes. This also says a lot for the other members of the collaboration to be this involved in communal activities where they sometimes compete, yet recognize the importance of providing a comprehensive set of tools and capabilities to their customers.

Semico agrees with the partners that the availability of such a comprehensive product in the marketplace will accelerate the introduction of silicon solutions at the 32nm and 28nm nodes by as much as one year. It will also help to reduce both design cycle time and design cost. While we need to wait a while before we see the direct impact of such a set of tools and process capabilities on the industry, it is safe to say that the SoC design environment is changing, and hopefully, for the better.

Rich Wawrzyniak
Sr. Analyst ASIC/SOC