Moore's Law Marches On

Next week Intel will be presenting several papers at the IEDM in San Francisco. Mark Bohr, Intel Senior Fellow and some of the research team previewed three of the topics being presented. The common theme through all three papers reflects Intel’s drive to push conventional technology as far as it will possibly go. The company feels that’s easier to do rather than introduce a whole new set of materials at this time. That being said, Intel also pursues new material research. The plan is to have options and solutions available and ready to implement when traditional silicon processing runs out of steam.

Following is a quick review of three papers that Intel will be presenting.

32nm Logic Technology

In September 2007, Intel announced their fully functional 32nm SRAM with a 0.18um² cell size. Today they are touting a 291Mbit SRAM, the same density as before, but with a 0.171um² cell size. This SRAM chip features greater than 1.9 billion transistors operating at 3.8GHz. Intel is on track for production readiness in Q4 2009.

One change that Intel is implementing with their 32nm process is the use of immersion lithography, one generation later than other manufacturers. There were no specific comments about any challenges or benefits of immersion technology, only that it was at the appropriate level of maturity for Intel. Although Intel stated there is still a lot of work to get 32nm technology into production, there is nothing out of the ordinary in the scope of work to have their 32nm process ready for production in 2009.

45nm Low Power SOC Technology

Intel’s CPU usually operates at leakage values of 10+ nanoamps per micron. SOC applications demand a much lower leakage. Intel has developed a derivative version of their 45nm high-k, metal gate process that can get the leakage values down to the 10 to 0.01 nanoamp per micron range. In addition to the low leakage, Intel added new device elements to accommodate all the analog circuitry that is usually added to an SOC.

One of the changes to the technology is a thicker dielectric as part of the gate insulating stack. This allows the transistor to operate at a higher than normal voltage. It also provides a wider range of I/O transistors and I/O types. And something that was not forgotten, an RFCMOS device element, that can accommodate the high frequencies that CMOS transistors can achieve.

As part of Intel’s ongoing research effort, the company is working with III-V materials such as Indium Antimonide to achieve voltage scaling while achieving the same performance at 10x power reduction. As a high mobility material, Intel has used InSb to cut voltages in half. The process involves building stacks on a GaAs wafer. There is a different lattice spacing at the bottom of the stack compared to the top. The ability to even explore these new options is made available because of the deposition techniques introduced at the 45nm technology node. Moving forward, Intel recognizes that a lot of work needs to be done to achieve comparable costs with silicon. In addition, Intel is also trying to reuse as much conventional design expertise as possible. Eventually Intel wants to transfer this to a silicon process.

-Joanne Itow