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Impressions of DAC 2011

I attended the 48th Design Automation Conference in San Diego this past week and I came away from the conference with several main thoughts:

  • EDA tool vendors continue to enhance their products by listening to their customers and acting on those inputs.
  • There is mounting evidence that the discussion centered around the trend towards IP Subsystems is real and has substance behind it.
  • The Automotive Networking workshop on Sunday featured a lively discussion around what networking bus would come after Ethernet.
  • There seems to be growing dissatisfaction around the limited amount of data showing silicon and software design costs for SoCs.

At this DAC conference several IP vendors and EDA tool vendors were discussing the term ‘IP Subsystem’ in their booths and in presentations and panel discussions given throughout the time I was there.

Some of the notable vendors discussing the concept were: Sonics, Synopsys, Cadence, Atrenta, ChipStart, and eSilicon to name a few.

The panel discussion hosted by Jim Hogan framed the issue succinctly: the requirement by mobile and portable devices to be able to stream video files has driven today’s SoC to become a collection of subsystems. In essence, the SoC of five to six years ago has now become a system level feature in today’s highly complex silicon solutions. This tremendous pace of integration can only be achieved through the use of IP – but this creates another problem for the designer; how to manage this integration process intelligently, efficiently and within cost and design time budgets. Increasingly, for many designers this has become very difficult to do. There needs to be a way to increase the level of complexity in response to market requirements without increasing the cost and amount of effort needed to accomplish the design beyond a reasonable level.

Enter the IP Subsystem!

Reducing the level of effort needed while increasing the complexity and functionality of the silicon is what is powering the move to IP Subsystems by many vendors as designers would rather design at the system functionality level instead of acquiring and assembling many discrete IP blocks to create the functionality they need.

This also opens the door for EDA companies to step up with new products and approaches to applications software design, testbench creation and integration of the requisite parts into a contiguous whole – a portion of the new business model the EDA industry has been seeking.

Semico has previously stated that we believe there will be an IP Subsystem product announcement from one or more of the major IP companies before the end of 2011. I saw nothing to change that view and it could even occur sooner than that. However, by way of full disclosure, this is not to say that the term IP Subsystem was a topic in every discussion occurring on the show floor. We are not quite there yet, but that time is not too far off. The momentum is building nicely and the DAC conference reinforced my opinion that this is really happening.

The timing of product introductions and the popularity of those products all depends on how much the market pressure on IP and EDA vendors to create innovative solutions in answer to the real world problems designers face rises before we see such a solution enter the marketplace.

I also attended the Automotive Networking Workshop on Sunday where several in-depth presentations were given on the current state of automotive data networks were given.

Many of today’s higher end cars are moving a good deal of data between their embedded processors and ASICs to deliver the creature comforts, safety and performance features we all have come to expect when we drive a late model vehicle today. however, all these features come with a price – higher data flows and more complex semiconductors to provide the performance we seek. The older automotive CAN and Flex-Ray buses are no longer up to the task of meeting these system requirements over the long term. Their days are numbered in the minds of many automotive designers.

What then comes next? Ethernet is one answer. However, cost was mentioned as a potential obstacle. A possible solution to this issue in creating a hybrid Ethernet standard to allow a lower data rate was also discussed. This may have some merit but I wondered how long it would take to hammer out such a standard. If it takes too long, we may be looking at needing the higher data rates Ethernet uses today.

A further point was made about what technology would come after Ethernet and that answer was ‘Wireless’.

While it would seem reasonable to predict a wireless network in an automotive application as the future networking choice by designers, in the presentations I saw (and I didn’t see all of them), nowhere was the word ‘Security’ mentioned once. I was told that, in a later session on another day which I did not attend, security was discussed, but I wanted to bring this up here to make the following point.

It seems to me and to Semico that the issue of Security is becoming more important over time yet there is little discussion of this in the engineering community (or maybe more accurately to say in the press) in general. It’s possible that the current discussion about security is limiter to only those applications that really need it like financial transactions, secure data networks, etc. This could be because many designers perceive that by adding security functions to their silicon solutions will add cost, increase power usage and ultimately degrade performance somewhat – all issues to be avoided.

However, the old adage, “the security is in the network,” is working less and less in the portable and mobile devices we are using. It seems to us that the same logic chain will apply to automotive networking, especially if the automotive industry implements a wireless networking technology. Security must be considered in this environment because of the importance an automobile can mean in certain situations.

Automotive companies extensively test their products to ensure they will work in harsh environments like Alaska or the Sahara desert when someone’s life may depend on a vehicle operating when the driver needs it to. Can the approach to ensuring their products are hack-proof and virus-resistant be any different when it comes to the security issue and the data buses that are implemented in future vehicle? Probably not!

Building in the right level of security from the beginning will be a lot easier than waiting until an ‘event’ of some sort forces a corrective action – and it will certainly be less expensive in the long run.

A very interesting data point mentioned in one of the presentations is that in today’s Mercedes ‘S’ class cars, no less than seven separate data buses are used. While it is true that this represents the high end of automobiles today, how long will it be before these high end features migrate downward to less expensive models? Given the rate of change in the automotive industry, it won’t be all that long.

One final impression of the conference was the ‘famous’ ITRS SoC design cost slide I mentioned at the beginning of this article. I found that many people are questioning the validity of this data and herein lays the problem.

While the data in the slide is accurate, several people mentioned to me that it is based on the inputs of only one company and only depicts the design costs from a single design!

As most of you know this slide is shown frequently at conferences, in company presentations and even in books and literature about the semiconductor industry. It is used by many people and companies as a means to tell a particular story or make a specific point. It is generally used as is: namely without stating any of the caveats that would normally accompany such a data point.

On the silicon design side of the equation the normal questions to ask of the data are:

  • Is it a first time effort at that process node?
  • Does it represent the most complex design at that process node?
  • Was every design parameter maxed out – biggest die, max number of transistors / gates, fastest clock speeds, number of CPU cores, etc.?
  • Does this data represent a mainstream part or a design for a niche application?
  • Do all the designs at a given node cost the same as shown by the data in the slide?

And finally:

  • From how many designs is this data derived?

This last point is key because while the data in the slide can be said to be accurate, just how many companies and designs is it accurate for? Semico does not believe we can use the data from one design and apply it to all other designs in the industry – especially when we see the cost curve this slide depicts spiraling out of sight for future nodes.

To say it is inaccurate is being very charitable at best!

The same could be said for the portion of the slide that shows software costs roughly equal or higher than the silicon design costs. Again, where are the caveats that put the data into context and provide perspective to the viewer?

On the Software design side some reasonable questions would be:

  • How many software designers does this design depict?
  • How long did the effort take to accomplish?
  • For software efforts, it is common to use many code developers to finish the design quickly. The more people used in the effort, the more costly it is. Where is this data and how does it relate to the design being shown? How does it relate to the rest of the industry?
  • How much code was reused from a previous effort? None? Some? Any?
  • How much of the depicted design cost was allocated for maintenance over the life of the product?

This last point is important since the companies writing their own applications programs probably do not use the same accounting rules that a software developer in the embedded software market uses. After all, most of these software applications are being written by semiconductor companies and not software development companies. Are there any differences between the two types of companies in how they account for development costs over time? Again, this data is not supplied with the slide.

This sort of data is becoming a critical part of the decision making process for many parts of the semiconductor supply chain.

  • When a SoC start-up goes out for funding, does the VC he interfaces with throw up this slide as an issue to be discussed? Is it a showstopper in the VCs mind?
  • When a company contemplates their next generation of silicon solution do they hesitate, thinking of this slide and the data it shows?
  • When an EDA company thinks about developing their next generation tool, do they wonder how big the customer base will be at the next process node given the increase in design costs shown by this data? Do they possibly delay their efforts until enough customers ask for new products?
  • Do the foundries look at the design cost data before they allocate their capex budget?
  • Do semiconductor companies hesitate before starting designs to enter new markets looking at how many parts they need to sell just to make back the design investment? Is the choice of market to enter gated by the design cost data shown in this slide?

The answer to all these questions is probably yes to some degree. While it is true that larger companies may not be totally influenced by design cost data, it is entirely likely that smaller companies would definitely pay attention to data points like this.

If these numbers are so important and are used to make so many important decisions in the industry, why is better data not available for everyone to see?

Unfortunately, the answer is simple. Not many companies are willing to share this data since, in the wrong hands, it would allow someone to calculate their competitors manufacturing costs with reasonable accuracy. Having that data would allow someone to know what their competitors bottom line threshold of pain would be in terms of how low they could go on a particular ASP price point. This would give a company a great advantage over their competition.

Not many people in the industry are willing to share their design cost data for these reasons.

This is an area that Semico is focusing on over the next month since it has implications that go throughout the industry. Stay tuned!

All in all, I can say that I thought this years DAC was very well run and that it seemed like attendance was up over last years conference. There was some blatant ‘over-the-top’ messages this year, but not more than in other years. If someone wanted to get the pulse of the EDA industry today, the DAC conference is definitely one place where that can be accomplished!

Rich Wawrzyniak, Senior Analyst

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