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IMPACT Conference Agenda

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7:30am – 8:30am Registration and Continental Breakfast
8:30am – 8:45am Welcome & Outlook – Jim Feldhan, Semico Research Corp.
8:45am – 9:25am Kurt Shuler, Arteris
9:25am – 10:10am Chris Rowen, Cadence
10:10am – 10:30am Break
10:30am – 12:00pm

Panel:  IP Ecosystem Solutions for Complex Systems
Moderator:  Mahesh Tirupattur, AnalogBits
Jason Polychronopoulos, Mentor Graphics
Warren Savage, IPextreme
Chris RowenCadence
Suk Lee, TSMC

12:00pm – 1:30pm Lunch – Sponsored by Tabula
Steve Teig, Tabula
  Afternoon Track 1: Semico Impact Afternoon Track 2: Hosted by Constellations
1:30pm – 2:00pm John Koeter, Synopsys Warren Savage, IPextreme
2:00pm – 2:30pm Robert Krohn, Cisco Gerard Rauwerda, Recore Systems
2:30pm – 3:00pm Break
3:00pm – 4:15pm

Panel:  Designing for New World Applications
Moderator: Kent Shimasaki, Infinitedge
Ron Moore, ARM
Grant Pierce, Sonics
Steve Singer, INSIDE Secure
John O'Neill, Skyworks

Andrew Levy, Ridgetop Group


Stephen Fairbanks, Certus Semiconductor

Michael Johnson, Atrenta

4:30pm – 5:30pm Reception – Sponsored by Cadence, IPextreme


Panel:  IP Ecosystem Solutions for Complex Systems

The race to deliver innovative market solutions and the increase in design complexity is facing the ultimate clash between priorities and resource allocation.  Is there any solution to curb the rising cost of IP integration?  This panel will address issues such as....

  • Software:  The amount of software included with the silicon or created to run on the silicon has increased dramatically. Correspondingly, the cost of the software creation effort has also increased, rising disproportionately compared to the silicon design effort in recent years.  How does the increase in the number of IP blocks in contemporary silicon designs influence the software design effort?
  • Verification:  Is it possible to rein in the time spent in Verification as a percent of total design time?  Do we need a new approach to the Verification effort?
  • Subsystems:  Have you looked at Subsystem IP as a potential solution to your next design challenge?  Can Subsystems deliver on the promise to reduce cost and time to market while providing adequate system-level functions?  How much of this is driven by customer requests versus innovative ideas within the EDA industry?

Panel:  Designing for New World Applications

Foundries are gearing up to ramp 20nm and 14nm process technology within a three-year window.  In addition to the high growth smartphone and tablet markets, there is a host of new applications on the horizon, including mobile medical and the Internet of Things (IoT) with its promise of massive unit volumes.  How can the IP ecosystem be a driver of these types of applications?

  • What changes are necessary to SoC designs between 20nm and 14nm and how will the IP ecosystem need to change to accommodate these increased transistor budgets?
  • How big a role is security IP destined to play in the new applications, and just how secure does the IoT need to be for users to feel comfortable in using its features?
  • How must power management IP be improved so that 50 billion mobile devices can operate in a cost effective environment?
  • How accurate do sensors need to be, and what levels of integration need to be reached for the new applications to provide the right level of functionality?
  • What are vendors requesting, and what are companies already doing to address these challenges?  

Limited sponsorship opportunities are still available. If you are interested in sponsoring, please contact Jim Feldhan or Joanne Itow.


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