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Capex Restraint Not Always a Bad Thing

A recent article by Peter Clarke, EETimes, ‘TSMC Overtakes Intel in Chip Capex Ranking’ seemed to imply that a lower capital expenditure in 2015 was a bad sign. A growing capital expenditure budget does not always signal good times ahead just as a small capex does not mean disaster. Most companies are talking about the slowing or end of Moore’s law. Intel is one of the few companies that is back on Moore’s Law transistor density curve with their 14nm second generation Tri-Gate process. In fact, Intel has publicly stated that at 14nm they are ahead of Moore’s Law! Increased transistor density typically means smaller die sizes. All other variables being equal, this also translates to higher yields and less wafers required to meet market demand. A reduced capex is one of the benefits of improved efficiencies when a process obtains its sweet spot. Is it possible that others have to spend more in capex in anticipation of larger die sizes, lower yields and the need for more wafer throughput? A growing capex could mean expanding sales or the promise of a new market, but declining capex is not necessarily a bad omen. Remember when the industry experienced huge crashes because of the cycles that were caused by capex overspending? We haven’t experienced one of those in a few years, but I’m sure that can’t be erased from our memories yet. In fact, a great example for restrained capex is the memory market. The big four memory companies have been enjoying an unprecedented three years of increased revenues due to a few years of prudent capex. Capex restraint is not always a universally bad thing.

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