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28nm Issues Generate Debate at Semico Summit

At the Semico Summit held May 2, 2011 in Phoenix, Az, one of the most lively discussions occurred during the panel Challenges at 28nm. Mahesh Tirupattur, Analog Bits brought out the best from the audience as well as panel members.

  • Chi-Ping Hsu, Sr VP, Research & Development, Silicon Realization Group, Cadence
  • Mark Papermaster, Vice President, Switching Silicon Technology Group, Cisco
  • Grant Pierce, President & CEO, Sonics
  • Suk Lee, Director, Design Infrastructure Marketing Division, TSMC

Some of the major issues and topics covered by the panelist were the following. Chi Ping Hsu, Cadence feels the 28nm technology node is challenging because of the techno-economic problems that first became apparent at the 45nm process node and have become even worse.  The EDA industry collectively must spend around $2B per year on R&D aimed at solving or removing obstacles to industry productivity, manufacturing predictability and company profitability. Despite all the issues, Suk Lee, TSMC currently has 89 28nm tape outs completed or in progress.  In addition, TSMC is making a big investment in 28nm.  The company expects to invest $16B in 28nm development and capacity. As vice president of Cisco’s Switching Silicon Technology Group, Mark Papermaster, has a first hand view of ASIC design and strategy.  Leakage power is now 50% of total power consumption. Many mobile vendors think 28nm will allow them to reduce power consumption.  Papermaster believes 28nm is a very fundamental process node but the industry solution requires a system level approach. Grant Pierce, Sonics has seen their role change over time. He agreed with Papermaster, Sonics is now being asked to address issues with a system level approach.  Customers want Sonics to operate more as a general contactor to pull the right types of IP together for a particular design. Audience participation was fueled by a question/statement from Len Perham, President and CEO, Mosys.   Designing products at and below 28nm are so costly and overall performance of chips is actually decreasing.  How can a company justify moving to 28nm when problems with yields and signal integrity reduce any scaling benefit?  There are too many roadblocks for most companies. According to Grant Pierce, it’s ‘invest or die’.  Suk Lee agreed that the investments are already being made by TSMC and others.  The key is to decrease risk and make the process more predictable by getting the IP and tool sets early so that the needed collaboration and verification have an opportunity to run their course. Aart de Geus, Chairman of the Board and CEO, Synopsys was in the audience and offered the following more optimistic view.  The same challenges and the same skepticism arose when the transition was made from 65nm to 45/40nm.  The challenges were overcome by the collaboration between engineers, designers and manufacturers.  He thinks the concern is overblown and that scaling roadblocks will continue to be overcome for digital designs into the 16/14nm process node.  He jokingly pointed out that the analog piece is a different issue and is Cadence’s problem. Grant Pierce agreed with de Geus that the roadblocks could be overcome, but the 28nm node will be a short lived node.  A ‘fab war’ will break out with the transition to smaller nodes. Designs in the mobile space are already looking to 22nm – to get even more power savings. Another question from the audience focused on 3D.  Is 3D an alternative to scaling or an enabler to scaling? TSMC:  Scaling will continue.  2.5D will provide opportunities for integration.  The goal is to mix and match the most appropriate IC dice.  3D will coexist with scaling. One of the means to continue on the Moore’s Law trend is 3D architectures.  Suk Lee believes that scaling will continue but will be aided by 3D. Cadence:  From a capability standpoint Cadence has done a lot of work with IDMs on 3D.  They remain cautious about adoption because of the cost of 3D.  The foundries are doing a lot of work expanding the ability of 3D. The issues are not about the technology or the design tools but industry infrastructure.  How do we deal with the bare die? Sonics:  The access to increased bandwidth using TSV technology is driving demand for 3D.  When the result is 4x performance at the same frequency and half the power, designers just can’t resist.  The next step is to developed multi-channel solutions, built into hardware to empower new chips with high bandwidth but invisible to software. Cisco:  3D is irresistible.  Silicon interposer is one solution and if this can come up the yield curve it will be an irresistible solution. The companies represented on the panel were definitely biased towards those with the ability to move to the next advanced technology solution.  They benefit from the companies willing to move up the technology curve.  But there were many companies in the audience that can’t afford to design at the bleeding edge or even be fast followers.  When all the bugs are worked out and economies of scale are reached, there use to be a group of fast followers providing a second wave of demand for the advanced IP, tools and capacity.  The concern is whether the fast followers or any followers are willing and able to move quick enough to provide the panelists a return on their investment. A possible solution to this “Catch 22” is the increasing use of derivative SoC designs to reduce cost and time to market. However, over-reliance on derivative designs does not address the fact that many of the current SoC architectures are getting rather old. A new round of effort to refresh these architectures must be started to ensure silicon solutions at 28nm can utilize all the features of 28nm while at the same time deliver all the features and functionality the markets will demand going forward. Based on what we are seeing today, Semico believes the process of architectural refresh has started and that it will accelerate over the next two years. Sam Caldwell, Analyst Joanne Itow, Managing Director, Manufacturing Rich Wawrzyniak, Sr. Market Analyst ASIC & SoC

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