During the week of June 16th, 2008 at the VLSI Technology Symposium, there were a lot of compelling papers presented. One in particular caught my attention because the findings had a very subtle underlying message. I’m referring to the Intel paper on floating body cell (FBC). The floating body cell is not new. Intel talked about a non-planar floating body cell in 2006. This year Intel touted a much smaller device using a planar design on SOI. The device could have 3-4x more bits per area. The benefit is faster computational rates.
It is well known that Intel does not currently use SOI for volume production. When considering the use of SOI for microprocessors, Intel has long claimed that its benefits diminished with each technology node shrink. The floating body cell announcement endorses the use of SOI but of course leaves a few openings for Intel to continue to walk a fine line around SOI. The buried oxide (BOX) thickness in Intel’s device is only 10nm compared to >100nm for many SOI uses. Intel feels that this technology is suitable for the 15nm node and beyond. IBM and ISS both have an SOI memory technology which they’ve shown as beneficial at 45nm and 32nm process technology.
