At the upcoming Embedded Systems Conference (April 2-4, 2007) Atmel will reveal details on the second generation of the 32-bit version of the AVR family, AVR32 UC3.
The AVR architecture was introduced by Atmel several years ago in the 8-bit MCU market. In recent years it has offered a 32-bit MCU version to aid its customers in a migration path, a strategy pursued by several MCU vendors.
Atmel’s latest development for AVR32 is optimized for low-power. One key feature is going to a three stage pipeline from the current seven stage. The single-cycle read/write SRAM is integrated into the core, thus it is in the pipeline. According to Atmel, with the SRAM having direct interface to the CPU that bypasses the system bus, the CPU is able to achieve faster execution.
Another key feature touted by Atmel to achieve low power and low cost is higher code density. This is achieved with an instruction set architecture (ISA) it shares with its AVR32 AP parent, but with over 220 instructions available as 16-bit compact and 32-bit extended instructions. The compiler automatically selects the most efficient compact or extended form of each instruction. Atmel also includes DSP functions.
The compact code also reduces the memory footprint required. The on-chip Flash is arranged in two banks to avoid wait state latency.
