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March 2007

SST All-in-One Memory

On Monday, SST announced an innovative new way to approach the memory requirements for a wide range of products. The All-in-OneMemory is a multi-chip package (MCP) consisting of three chips: NAND, RAM (DRAM or PSRAM), and a controller. The advantage this brings is the processor only needs a single RAM bus to interface with code storage, data storage, and RAM all at the same time. The type of RAM used depends on the density needed; under 512Mbit, they’ll use PSRAM. DRAM will be used for systems needing 512Mbit and more.

The NAND simulates NOR by using the RAM as a cache; SST calls this Pseudo-NOR, which is very appropriate because it is similar in concept to Pseudo RAM. This enables SST to offer execute-in-place (XIP), even though the system is based on NAND. The controller chip includes embedded NOR flash. The RAM is partitioned; part of it is used as cache, and part is used as system memory. Perhaps the most interesting aspect of the solution is the ability to partition part of the NAND as a memory-mapped ATA disk drive. The partitions are configurable so that system designers can customize the MCP to suit their needs.

Semico: MCU Memory Trends: How Much and What Kind

Microcontroller Market Analysis & Forecast

Phoenix, Arizona March 28, 2007 - The Microcontroller (MCU) market showed a slight recovery in 2006, growing 3.0% to reach $12.4 billion. This dollar growth was driven by the 32-bit and greater segment. Overall unit growth of MCUs was 19.5%.

Intel Blazes New Trail to Northeast China

Over the past few weeks the big semiconductor manufacturing buzz has been the rumors revolving around Intel’s next 300mm fab. On March 26th, Intel finally made it official. They will be locating their next greenfield fab in Dalian, China, a city in the Northeastern region of the country. Not only is this their first fab in Asia, its Intel’s first new location since 1992. The fab is expected to begin production in 2010, cost $2.5 billion and employ 1500. Initial production will be targeted at chipsets, processed on a technology node which will most likely be at least two generations behind Intel’s most advanced chips.

Semico Spin

Atmel Optimizing AVR for Low-Power 32-bit MCU Markets

At the upcoming Embedded Systems Conference (April 2-4, 2007) Atmel will reveal details on the second generation of the 32-bit version of the AVR family, AVR32 UC3.

The AVR architecture was introduced by Atmel several years ago in the 8-bit MCU market. In recent years it has offered a 32-bit MCU version to aid its customers in a migration path, a strategy pursued by several MCU vendors.

Atmel’s latest development for AVR32 is optimized for low-power. One key feature is going to a three stage pipeline from the current seven stage. The single-cycle read/write SRAM is integrated into the core, thus it is in the pipeline. According to Atmel, with the SRAM having direct interface to the CPU that bypasses the system bus, the CPU is able to achieve faster execution.

Another key feature touted by Atmel to achieve low power and low cost is higher code density. This is achieved with an instruction set architecture (ISA) it shares with its AVR32 AP parent, but with over 220 instructions available as 16-bit compact and 32-bit extended instructions. The compiler automatically selects the most efficient compact or extended form of each instruction. Atmel also includes DSP functions.

The compact code also reduces the memory footprint required. The on-chip Flash is arranged in two banks to avoid wait state latency.

Freescale 8-bit MCUs, Still a Market for Innovation and Growth

The high end of the MPU and MCU markets seem to always get so much more attention. Yet the 8-bit MCUs still account for huge volume. In 2006, 8-bit MCUs had $4.6 B in sales with shipments growing 5.3% to 4.2 billion units. It is a very competitive market driven by pricing. The 8-bit MCU ASPs declined 7.4% in 2006.

The key vendors driving growth in 8-bit MCUs are offering more features and memory at competitive prices. Automotive is the largest market for 8-bit MCUs. Chip vendors, like Freescale are looking to grow in other areas, in particular consumer and industrial applications. Last week Freescale announced the addition of the LC60 family to its long time successful S08 architecture.

The LC60 adds an integrated LCD driver to the S08. The MCU can be connected directly to an LCD without any additional circuitry. This is configurable for 4x40 or 3x41 segment displays including up to 16 alphanumeric displays. Freescale is offering memory options with 36KB and 60KB of Flash. The LC60 also features integrated communications interfaces: SCI, two SPI modules and inter-IC bus module. This enables connecting the MCU to external power measurement ICs or to ZigBee modules.

Discera Announces a New Vibration: MEMS-Based Oscillators

On Monday, February 26, Discera, Inc., a San Jose, CA company announced the availability of its MOS1 MEMS-based oscillator series, which is being sampled now with volume production expected this summer. These oscillators have a MEMS resonator and an ASIC embedded within a conventional QFN package or ceramic package. They can be used as a direct replacement for quartz crystal oscillators, which are the key timing element in virtually all electronic systems. There are thousands of applications, sometimes with volumes in the millions. The MEMS-based oscillators have many advantages, when compared to quartz crystal oscillators:

The first advantage is lower cost. The MEMS-based oscillators will enter the market at less than half the cost of crystal oscillators, and cost reductions are on their roadmap. Profit margins for crystal oscillators are very thin, and there is no foreseeable way to significantly reduce costs or margins.

SOI Embedded DRAM Boosts Performance of IBM Multi-Core Processors

At the International Solid State Circuits Conference being held in San Francisco this week, IBM Corp. is announcing an on-chip memory technology that it claims has the fastest access times ever recorded for embedded DRAM. IBM expects this technology to be a major step forward in solving the multi-core processor memory bottleneck.

IBM said its solution entails swapping out most of the embedded SRAM cache used to store information directly on computer chips and replacing the SRAM cells with embedded DRAM designed with silicon-on-insulator (SOI) technology. IBM says the technology effectively doubles microprocessor performance beyond what classical scaling alone can achieve and vastly improves microprocessor performance in multi-core designs and graphics applications.

IBM’s paper describes a 65nm prototype embedded DRAM with a latency of 1.5 ns and a cycle time of 2 ns. This memory performance is an order of magnitude faster than today's DRAMs and competitive with embedded SRAM that is typically used for microprocessor cache memory.

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