You are here

February 2007

CHARTERED AND SAMSUNG EXECUTIVES TO JOINTLY DISCUSS COLLABORATIVE MODEL FOR ADVANCED MANUFACTURING AT SEMICO SUMMIT

Phoenix, Arizona February 26, 2007 - Chia Song Hwee, president and CEO of Chartered Semiconductor Manufacturing, and Dr. Kwangpyuk “K.P.” Suh, executive vice president, Systems LSI Technology Development at Samsung, will jointly present “Customer-focused Collaboration to Address Unprecedented Design and Manufacturing Challenges” during the upcoming Semico Summit.

Still Good Advice: Don’t Put All Your Fabs in One Basket

Last week, NEC Electronics America held an open house to showcase their newly expanded and upgraded fab in Roseville, CA. The fab has added an 8-inch line to the already existing 6-inch facility. This is all part of NEC Electronics Multifab™ strategy which was unveiled in February 2006. The Multifab strategy is designed to streamline manufacturing, enhance quality control and ensure a secure product supply by enabling customers to qualify one process at multiple manufacturing facilities. The process that will be ready for production later this year is an exact copy of a process that is already running in NEC Electronics Kyushu and Kumamoto facilities.

The increased capacity and capability is part of NEC Electronics’ plan to become the number one automotive microcontroller supplier by 2010. In addition to adding 0.15-micron, 8-inch wafer capacity, NEC Electronics is increasing resources at development centers in Dallas, Texas and Duesseldorf, Germany.

Semico Spin

Intel TeraFlop Research Chip: A Glimpse of Things to Come

This week Intel announced a test chip for its Terascale Computing Research program. The objective is to eventually bring super-computing into mainstream computing.

The Teraflops Research Chip is an 80 core design. Keep in mind that this is not an MPU architecture ready for commercialization but a test vehicle. An individual core does not have the same capability as the current complex cores in the 80x86 architecture. They are relatively simple in design.

A tile includes a compute element and a router to connect to each nearest neighbor and to an SRAM chip in the “z” direction. The SRAM chip is a stacked memory above the MPU. The actual processing element consists of data memory, instruction memory, and two floating point engines. Any tile can communicate with any other tile via the router, 80 GB/sec. This is NOT an IA instruction set (standard x86) but a VLIW. This 80-core chip is NOT a product but a research vehicle. The research chip has 100 million transistors and is manufactured on Intel’s standard 65nm process.

A key feature is the clocking scheme. Intel calls it mesochronous clocking. This is a modular clock as opposed to a single global clock. It allows for a fine grain power management thereby saving power. Intel claims energy efficiency of 16 gigaflops/watt.

Intel is exploring important technologies and techniques with this. Among these are

Freescale Symphony Dual-Core DSPs Provide Economical HD Audio Performance

Freescale Semiconductor has announced two dual-core DSP (Digital Signal Processing) chips designed to support multiple HD (High Definition) audio standards. These two chips, the Symphony DSP56720 and DSP56721, are the first offerings in what will become a family of multi-core 24-bit audio processors, which will be suitable for audio applications in headphones, rack-mounted amplifiers, automotive sound systems or even in professional audio systems.

HD audio standards are requiring increased processing power and memory. To meet these requirements, many of today’s high performance audio solutions use multiple DSPs. The Symphony DSP56720 and DSP56721 use dual DSP56300 24-bit cores. Each core operates at 200 MIPs with a 200 MHz clock, thus providing all the processing power needed on one chip in one package, reducing board space and the cost of the design. The capability for increased memory is also included.

Twitter