This week Intel announced a test chip for its Terascale Computing Research program. The objective is to eventually bring super-computing into mainstream computing.
The Teraflops Research Chip is an 80 core design. Keep in mind that this is not an MPU architecture ready for commercialization but a test vehicle. An individual core does not have the same capability as the current complex cores in the 80x86 architecture. They are relatively simple in design.
A tile includes a compute element and a router to connect to each nearest neighbor and to an SRAM chip in the “z” direction. The SRAM chip is a stacked memory above the MPU. The actual processing element consists of data memory, instruction memory, and two floating point engines. Any tile can communicate with any other tile via the router, 80 GB/sec. This is NOT an IA instruction set (standard x86) but a VLIW. This 80-core chip is NOT a product but a research vehicle. The research chip has 100 million transistors and is manufactured on Intel’s standard 65nm process.
A key feature is the clocking scheme. Intel calls it mesochronous clocking. This is a modular clock as opposed to a single global clock. It allows for a fine grain power management thereby saving power. Intel claims energy efficiency of 16 gigaflops/watt.
Intel is exploring important technologies and techniques with this. Among these are
