What I Learned on the Way to the Semico Impact Conference: Focus on the IP Ecosystem

I had a very interesting discussion with Sundar Iyer, CEO of Memoir Systems, during a briefing they gave Semico on their just-released Pattern Aware Memory IP technology.

To briefly restate their announcement: Memoir has researched the different interactions between processors and memory in high-performance datacom systems and found that certain operations recur fairly often.  These operations roughly fall into four groupings: Counter Memory, Sequential Memory, Allocation Memory and Update Memory.  There are probably many more than these types, but Memoir is starting with these operations to begin with.

Memoir Systems is a 3^rd party memory IP company and, as such, devotes its time to developing and introducing embedded memory IP to the market. In the case of this new product announcement, the memory IP they are introducing is tailored around the four functions mentioned above. In other words, their memory IP is now configured to better support these specific operations at the memory level and not through software at the processor level in the system. This has large implications for system performance and throughput.

One of the most pressing issues SoC designers and system architects face today is the growing problem of the processor–memory bottleneck.  Designers can keep adding more memory to increase system performance, but at diminishing returns, mostly because memory performance has not kept pace with processor performance over time.  New memory architectures have been introduced by discrete DRAM vendors.   Products such as synchronous DRAM, starting in the early1990s, evolving to double data rate (DDR) II, III, IV and beyond, help deal with this issue.

In the discrete memory world there is reluctance to ‘tinker’ with device architectures to fine-tune them to solve specific problems.  The old adage about DRAM being ‘cheap and dense like bricks’ is as true today as it was back in the 1980s.  In order to arrive at the absolute lowest device cost, discrete memories must be kept as similar to one another as possible, and this rules out having many different variants in the market at any one time. However, in the embedded memory world, this has less significance because this memory, by its embedded nature, is essentially custom every time a SoC designer crafts the design. This opens the door for a fair bit of fine-tuning by the designer to solve issues specific to the design.

While a better solution than using discrete memory, embedded memories up to this point have offered a ‘one-size-fits-all’ approach with little differentiation possible unless the designer creates a custom design. This is possible, but at the cost of additional time and effort on the designer’s part. In essence, the designer must identify the new memory operations needed, add them to the design in the form of creating specific memory architectures to solve the problem and then create the software to manage them at the processor or operating system level. This is a considerable amount of work.

Enter Memoir Systems, who has taken this idea further by offering memory types already configured to perform certain types of system-level operations. This relieves the designer from needing to configure a memory solution to perform these functions. In addition, because the memory is created this way from the start, the need to create and run software operations through the processor to achieve the same results is removed from the design, providing a benefit to the designer.

This approach is very interesting because Memoir has identified several different types of memory-processor operations and has created memories that perform these functions in the normal course of their operation within the system – very innovative. And in addition, this approach can save designers and device architects a considerable amount of die area, producing tangible power savings while increasing device performance – again, very desirable.

In my opinion, further exploration of this type of solution could yield additional innovation in the way SoC designers construct their silicon solutions and allow completely different device architectures to be created from what we see in the market today.  This can have far-ranging impacts on the SoC design community in the long run and is another example of how the 3^rd party IP market aids the SoC market and the larger semiconductor market – through innovative ideas made real using licensable IP.  The industry continues to benefit from their efforts, which benefit us all.